When EG is fairly large and negative, the JFET is pinched off, and no current flowsthrough the channel. As EG gets less negative, the channel opens up, and current be-gins flowing. As EG gets still less negative, the channel gets wider and the current ID in-creases. As EG approaches the point where the SG junction is at forward breakover, thechannel conducts as well as it possibly can.If EG becomes positive enough so that the SG junction conducts, the JFET will nolonger work properly. Some of the current in the channel will then be shunted offthrough the gate, a situation that is never desired in a JFET. The hose will spring a leak!The best amplification for weak signals is obtained when the gate bias, EG, is suchthat the slope of the curve in Fig. 23-5 is the greatest. This is shown roughly by therange marked X in the figure. For power amplification, however, results are often bestwhen the JFET is biased at, or even beyond, pinchoff, in the range marked Y.The current ID passes through the drain resistor, as shown in either diagram of Fig.23-4. Small fluctuations in EG cause large changes in ID, and these variations in turnproduce wide swings in the dc voltage across R3 (at A) or R4 (at B). The ac part of thisvoltage goes through capacitor C2, and appears at the output as a signal of muchgreater ac voltage than that of the input signal at the gate. That’s voltage amplification.Drain current versus drain voltageYou might expect that the current ID, passing through the channel of a JFET, would in-crease linearly with increasing drain voltage ED. But this is not, in general, what hap-pens. Instead, the current ID rises for awhile, and then starts to level off.The drain current ID (which is the same as the channel current) is often plotted asa function of drain voltage, ED, for various values of gate voltage, EG. The resulting set ofDrain current versus drain voltage42123-5Relative draincurrent as a functionof gate voltage for ahypotheticalN-channel JFET.