4.12 Practical Considerations in Transistor Layout

Chapter 4.12 Practical Considerations in Transistor Layout

Radio Frequency Integrated Circuit Design Second Edition Book
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Radio Frequency Integrated Circuit Design Second Edition Book

  • 98 A Brief Review of Technologygm stops increasing, the noise figure no longer falls and because g is increasing, noise figure actually starts to rise at high overdrive voltages and the shape of the curve approximately matches that of the simulation. By performing a noise summary it was determined that the remaining discrepancy is due mainly to 1/f noise and noise due to source and substrate resistances. In Chapter 7, it will be shown how to use scaling and matching to achieve con-siderably lower noise than shown in this example. 4.12  Practical Considerations in Transistor Layout4.12.1  Typical Transistors A typical layout for a transistor is shown in Figure 4.23.Typically standard transistors have been optimized for the highest-frequency response, fast switching, and compact size for digital circuits. However, most pro-cesses also have low and high threshold devices. Low threshold devices may have higher leakage when off, but allow for operation at very low supply voltages. Higher threshold transistors are built with thicker gate oxide; hence, will have higher breakdown voltage, especially useful in the design of power amplifiers. However, with thicker oxide, typically minimum gate lengths are not allowed, hence the fT is reduced so higher breakdown voltages come at the expense of frequency response. Another option is the triple well transistor. As discussed previously, triple well tran-sistors will minimize the body effect and hence it is easier to build followers with better drive capability. In terms of matching, proximity is important. Transistors in their own separate wells will be further apart hence matching can be worse.4.12.2  SymmetryIn differential circuits, symmetry is very important to ensure that unwanted cou-pling into both sides of the circuit is equal. This means the coupled signal will be Figure 4.23  Layout for CMOS transistor with four fingers.