Radio Frequency Integrated Circuit Design Second Edition Book

Radio Frequency Integrated Circuit Design Second Edition Book
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Radio Frequency Integrated Circuit Design Second Edition Book

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    Radio Frequency Integrated Circuit DesignSecond Edition

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    For a list of recent related titles in the Artech House Microwave Library, please turn to the back of this book.

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    Radio Frequency Integrated Circuit DesignSecond EditionJohn W. M. RogersCalvin Pletta r t e c h h o u s e . c o m

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    Library of Congress Cataloging-in-Publication DataA catalog record for this book is available from the U.S. Library of Congress.British Library Cataloguing in Publication DataA catalogue record for this book is available from the British Library.ISBN-13: 978-1-60783-979-8Cover design by Igor Vald...

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    ContentsF 14,oreword 14, to 14, the 14, First 14, Edition 14, 14,xiii 18,Preface 18, 18,xii 20,Acknowledgments 20, 20,xix 22, ChaptER 22, 1 22, 22,Introduction 22, to 22, Communicatio 22,ns 22, Circuits 22, 22,1 22,1.1 22, 22,Introduction 22, 22,1 23,1.2 23, 23, Lower Frequency Analog De...

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    59,2.4.3 59, 59,Minimum Shift Keying (MSK) 59, 59,38 7,2.4.4 7, 7,Quadrature Amplitude Modulation 7,(QAM) 7, 7,39 61,2.4.5 61, 61,Orthogonal Frequency Division Multiplexing (OFDM) 61, 61,40 61,References 61, 61,40 64,ChaptER 64, 3 64, 64,System 64, Level 64, Architecture 64, and 64,...

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    Contents ii 110,4.11.1 110, 110,NMOS Transistor Operation 110, 110,89 111,4.11.2 111, 111,PMOS Transistor Operation 111, 111,90 111,4.11.3 111, 111,CMOS Small-Signal 111,Model 111, 111,90 113,4.11.4 113, 113,fT 113, and fmax 113, for CMOS Transistors 113, 113,92 113,4.11.5 113, ...

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    165,6.14 165, 165,The Quality Factor 165,of an Inductor 165, 165,144 169,6.15 169, 169,Characterization of an Inductor 169, 169,148 170,6.16 170, 170,Some Notes about the Proper Use 170,of Inductors 170, 170,149 173,6.17 173, 173,Layout of Spiral Inductors 173, 173,152 174,6.18 174...

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    Contents ix 235,7.5 235, 235,Stability 235, 235,214 236,7.6 236, 236,Differential Amplifiers 236, 236,215 236, 236,7.6.1 236, 236,Bipolar Differential 236,Pair 236, 236,215 238,7.6.2 238, 238,Linearity in Bipolar Differential 238,Pairs 238, 238,217 239,7.6.3 239, 239,CMOS Diff...

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    292,8.11.2 292, 292,Generating 90° Phase Shift 292, 292,271 295,8.11.3 295, 295,Image Rejection with 295,Amplitude and Phase Mismatch 295, 295,274 297,8.12 297, 297,Alternative Mixer Designs 297, 297,276 298,8.12.1 298, 298,The Moore Mixer 298, 298,277 298,8.12.2 298, 298,Mix...

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    Contents xi 368,9.19 368, 368,Low-Frequency Phase-Noise Upconversion 368,Reduction Techniques 368, 368,347 368, 368,9.19.1 368, 368,Bank Switching 368, 368,347 370,9.19.2 370, 370,gm 370, Matching and 370,Waveform Symmetry 370, 370,349 371,9.19.3 371, 371,Differential Varactors a...

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    463,11.3 463, 463,Efficiency Calculations 463, 463,442 464,11.4 464, 464,Matching Considerations 464, 464,443 464, 464, 464,11.4.1 464, 464,Matching to S22* Versus 464,Matching to 464,Gopt 464, 464,443 465,11.5 465, 465,Class A, B, and C Amplifiers 465, 465,444 473,11.5.1 4...

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    xiiiForeword to the First EditionI enjoyed reading this book for a number of reasons. One reason is that it addresses high-speed analog design in the context of microwave issues. This is an advanced level book, which should follow courses in basic circuits and transmission lines. Most analog inte...

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    This worked fairly well with some analog circuits at audio frequencies, but failed completely in the progression to integrated circuits.In high-speed IC design nowadays, the computer-based circuit simulator is cru-cial. Such simulation is important at four levels. The first level is the use of si...

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    money by facilitating the early success of applications. This book can be beneficial to designers—or to those less focused on specific design—to recognize key con-straints in the area, with faith (justified, I believe) that the book is a correct picture of the reality of high speed RF communi...

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    xiiPrefaceFor this second edition of this book, we have added significantly more information about radio frequency integrated circuit (RFIC) design using complementary metal oxide semiconductor (CMOS) transistors, whereas the first edition strongly empha-sized design with bipolar transistors. Sin...

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    xixAcknowledgmentsThe first edition of this book evolved out of a number of documents including tech-nical papers, course notes, and various theses. We decided that we would organize some of the research we and many others had been doing, and turn it into a manu-script that would serve as a compr...

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    c h a p t e r 1Introduction to Communications Circuits1.1  IntroductionRadio frequency integrated circuit (RFIC) design is an exciting area for research or product development. Technologies are constantly being improved, and as they are, circuits formerly implemented as discrete solutions can n...

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    Introduction to Communications Circuits1.2   Lower Frequency Analog Design and Microwave Design Versus Radio-Frequency Integrated Circuit DesignRadio-frequency integrated circuit design has borrowed from both analog design techniques, used at lower frequencies [4, 5], a...

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    Assuming a sinusoidal voltage waveform, Pwatt is given by 2rmswattvPR= (1.2)where R is the resistance the voltage is developed across. Note also that vrms can be related to the peak-to-peak voltage vpp by pprms2 2vv= (1.3)Similarly, noise in analog signals is often defined in terms of volts or am...

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    Introduction to Communications CircuitsIn summary, as stated earlier, RF design is a combination of techniques used in low-frequency analog design, and techniques used in traditional microwave design. On chip if distances between components are small, some analog design concepts are used. That i...

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    . Overview LNA amplifies the input signal without adding much noise. The input signal can be very weak, so the first thing to do is strengthen the signal without corrupting it. As a result, noise added in later stages will be of less importance. The image filter that follows the LNA removes out-o...

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    Introduction to Communications Circuitsmixers, voltage-controlled oscillators (VCOs), and power amplifiers. Synthesizers will be discussed in Chapter 10.References [1] Lee, T. H., The Design of CMOS Radio Frequency Integrated Circuits, 2nd ed., Cam-bridge, U.K.: Cambridge University Press, 2004....

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    c h a p t e r 2Issues in RFIC Design: Noise, Linearity, and Signals2.1  IntroductionIn this chapter we will have a brief look at some general issues in RF circuit design. The nonidealities we will consider include noise and nonlinearity. An ideal circuit, for example an amplifier, produces a pe...

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    Issues in RFIC Design: Noise, Linearity, and SignalsTo find the total noise due to a number of sources, the relationship of the sources with each other has to be considered. The most common assumption is that all noise sources are random and have no relationship with each other, so they are said...

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    2.2 Noise outPkTB= (2.5)2.2.3  Available Power from AntennaThe noise from an antenna can be modeled as a resistor [5]. Thus, as in Section 2.2.2, the available power from an antenna is given by: -== ´21available4 10W / HzPkT (2.6)at T = 290K, or in dBm/Hz: --æö´== -ç÷´èø21availa...

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    10 Issues in RFIC Design: Noise, Linearity, and SignalsThus, we can now also formally define signal-to-noise ratio. If the signal has a power of S then the SNR is: SNRNoise FloorS= (2.10)Thus, if the electronics added no noise and if the detector required a signal-to-noise ratio (SNR) of 0 dB, th...

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    2.2 Noise 11This shows that the minimum possible noise factor, which occurs if the electron-ics adds no noise, is equal to 1. Noise figure, NF, is related to noise factor, F, by: 10NF 10log F= (2.15)Thus, while the noise factor is at least 1, the noise figure is at least 0 dB. In other words, an ...

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    12 Issues in RFIC Design: Noise, Linearity, and Signalsoutput of the circuit due to all resistors and then determine the circuit noise figure and signal-to-noise ratio assuming a 1-MHz bandwidth and the input is a 1-V sine wave.Solution: In this example, at vx the noise is still due to only RS an...

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    2.2 Noise 13 520log117.9 dB6.392 nV1 MHzHzSNæöç÷==ç÷ç÷×èøThis example illustrates that noise from the source and amplifier input resis-tance are the dominant noise sources in the circuit. Each resistor at the input pro-vided 4.5 nV / Hz, while the two resistors behind the amplifier eac...

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    14 Issues in RFIC Design: Noise, Linearity, and Signals2.2.5  The Noise Figure of an Amplifier CircuitWe can now make use of the definition of noise figure just developed and apply it to an amplifier circuit [8]. For the purposes of developing (2.14) into a more useful form, it is a...

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    2.2 Noise 15In addition, the correlated components will be related by the ratio: cc ciY v= (2.21)where YC is the correlation admittance. Note that we have provided both correlated and uncorrelated terms for both voltage and current, as well as the correlation admittance. These terms are not all ...

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    16 Issues in RFIC Design: Noise, Linearity, and Signals optc ccuR BBRR-=+ (2.30)2.2.6  Phase NoiseRadios use reference tones to perform frequency conversion. Ideally, these tones would be perfect and have energy at only the desired frequency. Unfortunately, any real signal source will have en...

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    2.2 Noise 1Assume the phase fluctuation is of a sinusoidal form as: ( )sin()npmttϕϕω= (2.32)where fp is the peak phase fluctuation and wm is the offset frequency from the car-rier. Substituting (2.32) into (2.31) gives: ωϕωωϕωωϕωéù=+ëûéù=-ëûout0LO0LOLO( )cossin()cos()cos(sin(...

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    1 Issues in RFIC Design: Noise, Linearity, and Signalswhere f2rms is the rms phase-noise power density in units of [rad2/Hz]. Note that single-sideband phase noise is by far the most common type reported and often it is not specified as SSB, but rather simply reported as phase noise. However, alt...

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    2.3 Linearity and Distortion in RF Circuits 1as shown in Figure 2.7(b). However, if the circuit is not biased between the two clipping levels, then clipping can be nonsymmetrical as shown in Figure 2.7(c).2.3.1  Power Series ExpansionMathematically, any nonlinear transfer function can be wr...

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    20 Issues in RFIC Design: Noise, Linearity, and SignalsTo describe the nonlinearity perfectly, an infinite number of terms is required; however, in many practical circuits the first three terms are sufficient to characterize the circuit with a fair degree of accuracy.Symmetrical saturation as sho...

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    2.3 Linearity and Distortion in RF Circuits 21where second-order terms are comprised of second harmonics HD2, and mixing components, here labeled MIX, but sometimes labeled IM2 for second-order inter-modulation. The mixing components will appear at the sum and difference frequen-cies of the two i...

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    22 Issues in RFIC Design: Noise, Linearity, and SignalsExample 2.4: Determination of Frequency Components Generated in a Nonlinear SystemConsider a nonlinear circuit with 7-MHz and 8-MHz tones applied at the input. Determine all output frequency components, assuming distortion components up to th...

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    2.3 Linearity and Distortion in RF Circuits 23can be compared to the third-order intermodulation term given by: 333IM34ik v= (2.53)Note that for small vi, the fundamental rises linearly (20 dB/decade) and the IM3 terms rise as the cube of the input (60 dB/decade). A theoretical voltage at which t...

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    24 Issues in RFIC Design: Noise, Linearity, and SignalsOf course, the third-order intercept point cannot actually be measured directly, since by the time the amplifier reached this point, it would be heavily overloaded. Therefore, it is useful to describe a quick way to extrapolate it at a given ...

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    2.3 Linearity and Distortion in RF Circuits 25Assume that a device with power gain G has been measured to have an output power of P1 at the fundamental frequency and a power of P2 at the IM2 frequency for a given input power of Pi, as illustrated in Figure 2.10. Now, on a log plot (for example wh...

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    26 Issues in RFIC Design: Noise, Linearity, and SignalsThus, the 1-dB compression point can be found by substituting (2.69) and (2.70) into (2.68): 31 1dB3 1dB1 1dB340.89125k vk vk v+= (2.71)Note that for a nonlinearity that causes compression, rather than one that causes expansion, k3 has to be ...

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    2.3 Linearity and Distortion in RF Circuits 2 13IP31dB1323 ||5.250.22||kkvvkk== (2.77)Thus, these voltages are related by a factor of 5.25 or about 14.4 dB.Thus, one can estimate that for a single tone, the compression point is about 10 dB below the intercept point, while for two tones, the 1-dB ...

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    2 Issues in RFIC Design: Noise, Linearity, and SignalsIf we take three of these signals, then the third-order nonlinearity gets a little more complicated than before:33332222221232311321 2 3123112323TBHD3IM3()3333336xxxxxxx xx xx xx xx xx xx x x++=+++++++++ �������������...

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    2.4 Modulated Signals 2The CSO is similar to the CTB, and can be used to measure the linearity of a broadband system. Again, if we have N signals all at the same power level, we now consider the second-order distortion products of each pair of signals that falls at frequencies w1 ± w2. In this c...

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    30 Issues in RFIC Design: Noise, Linearity, and Signalstion across the link. This process is called modulating the carrier. Usually in radio frequency communication systems, the bandwidth that the data occupies is a small fraction of the frequency at which it is transmitted. There are many types ...

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    2.4 Modulated Signals 31Thus, the ratio of Es to the PSD of the noise No is given by ×==×sssoES TS BWNNNfBW (2.89)Thus, the ratio of the energy per symbol to the noise density is equal to the signal-to-noise ratio of the radio if the radio channel bandwidth is equal to the sym-bol frequency. T...

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    32 Issues in RFIC Design: Noise, Linearity, and Signalsnot treated separately as it can be understood to be a subset of phase modulation. Some modulation schemes only change the amplitude of the signal and some only change the phase (or frequency) of the signal, but some more complicated modula-t...

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    2.4 Modulated Signals 33A very important feature in this figure is that adjacent symbols differ by only one bit. This means that if a phase is misinterpreted, a minimum number of bit errors will occur. One additional refinement that is sometimes implemented with QPSK is to de-lay one of the baseb...

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    34 Issues in RFIC Design: Noise, Linearity, and Signalserror has been made). If the noise changes the phase by more than this amount, the symbol will be incorrectly interpreted. Note that as long as only one bit changes when an adjacent phase is incorrectly interpreted, the bit error rate as a fu...

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    2.4 Modulated Signals 35Example 2.6: The Required Noise Figure of a Radio A receiver must be able to detect a signal at a power level of -95 dBm with a bit error rate of 10-3. The channel is 1 MHz wide at baseband and two modulation formats are used. One is BPSK and the other is 8-PSK. Determine ...

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    36 Issues in RFIC Design: Noise, Linearity, and Signals2.4.2  Frequency ModulationIn PSK modulation, the phase of the carrier is changed as a means to transmit infor-mation. On the other hand, a frequency shift keyed (FSK) modulated signal encodes data by changing the frequency of the carrier...

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    2.4 Modulated Signals 3bits/sec/Hz? Remember that the signals (centered at their carrier frequencies) will have a power spectral density similar to that shown in Figure 2.12. Thus, adjacent frequencies must be spaced so that there is minimal interference between different bits. A way to do this i...

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    3 Issues in RFIC Design: Noise, Linearity, and SignalsNote that with FSK the bit error probability is related to the symbol error prob-ability by: / 21BsMPPM=×- (2.103)Therefore the probability of bit error is given by: ,2ssBooEMEPMQNNæöæö £×ç÷ç÷èøèø (2.104)2.4.3  Minimum Shif...

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    2.4 Modulated Signals 3higher or lower than the nominal carrier frequency for that bit period. Note that MSK is very similar to BFSK except that the two frequencies in MSK are spaced at half the separation compared to BFSK. This means that MSK is more spectrally ef-ficient than BFSK. Also, note t...

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    40 Issues in RFIC Design: Noise, Linearity, and Signals2.4.5  Orthogonal Frequency Division Multiplexing (OFDM)OFDM is a designed to help improve the link performance in a radio link where there can be frequency selective fading or interference within the bandwidth of the channel. The i...

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    2.4 Modulated Signals 41 [2] Sze, S. M., Physics of Semiconductor Devices, 2nd ed., New York: John Wiley & Sons, 1981. [3] Gray, P. R., et al., Analysis and Design of Analog Integrated Circuits, 4th ed., New York: John Wiley & Sons, 2001. [4] Stremler, F. G., Introduction to Communicat...

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    4343c h a p t e r 3System Level Architecture and Design Considerations3.1   Transmitter and Receiver Architectures and Some Design Considerations 3.1.1  Superheterodyne Transceivers A block diagram of a typical superheterodyne radio transceiver using air as a medium is s...

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    44 System Level Architecture and Design ConsiderationsFor high-side injection: IFLORFfff=- (3.2)Since the IF stage is at a fixed frequency, the synthesizer must be made program-mable so that it can be tuned to whatever input frequency is desired at a given time. An input signal at an equal distan...

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    3.1 Transmitter and Receiver Architectures and Some Design Considerations 45the IF, and possibly some subset of the original adjacent channels depending on the quality of the filter used. Usually, automatic gain control (AGC) amplifiers are also included at the IF. They adjust the gain of the rad...

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    46 System Level Architecture and Design Considerationsfrequencies is much more difficult than doing so at the IF. Since the LO signal is now at the same frequency as the incoming RF signal, LO energy can couple into the RF path and cause problems. Without an IF stage, more gain and gain control m...

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    3.1 Transmitter and Receiver Architectures and Some Design Considerations 473.1.3  Low IF Transceiver and Other Alternative Transceiver ArchitecturesOne alternative architecture is called a low IF transceiver. The low IF architecture sees most of its advantage on the receive side....

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    48 System Level Architecture and Design Considerationswell at IF), but also removes the need for the extra synthesizer, potentially reducing layout area and power dissipation.3.2  System Level ConsiderationsThe next subsections will discuss some of the most important design considerations w...

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    3.2 System Level Considerations 49a stage by itself. For this reason, we typically design systems with a low noise amplifier at the front of the system. We note that the noise figure of each block is typically determined for the case in which a standard input source (e.g., 50W) is connected. The ...

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    50 System Level Architecture and Design ConsiderationsSolution: Since the bandwidth of the system has been given as 200 kHz, the noise floor of the system can be determined:= -+= -10Noise Floor174 dBm 10log (200,000)121 dBmWe make use of the cascaded noise figure equation and determine that the o...

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    3.2 System Level Considerations 51 ++++=== ++++= += ++++………2222232()()1222(total)11222(source)()()222321222112222123222112111nnni addedni sourcenisvvvini sourceni sourcesnnnvvvsnnnss vs vvvvvvvNRGG GFNvvRvvvGG GkTRvvvkTRkTR GkTR G G (3.14)This formula would provide the system designer with ...

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    52 System Level Architecture and Design Considerations==-Þ=-=´=´=230.6(1)(1)442.76 0.9 nV 2.49 nV / HznVGAVGAnVGAsssvNFkTvFkTRkTRRIf the same noise current is now fed into 5W||5 kW instead of 50W||5 kW, the noise voltage will be approximately 1/10 since in either case the 5 kW resistor can be ...

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    3.2 System Level Considerations 53Now applying the definition of IIP3 to the overall transfer function yields: 11IIP33132123123 |2|abbabaabak kvk kk k kk k=++ (3.18)Now if both sides are squared and inverted this becomes:3313212313113212211111111IIP32213344babaababababaaababababk kk k kk kk kk kk...

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    54 System Level Architecture and Design ConsiderationsIn general, the IIP2 of cascaded stages will be given by: =+++ …112IIP2IIP2 _1IIP2 _ 2IIP2 _ 311vvvAA Avvvv (3.26)3.2.3  Dynamic RangeSo far, we have discussed noise and linearity in circuits. Noise determines how small a signal a receiv...

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    3.2 System Level Considerations 55Solution: The overall receiver has a gain of 19 dB. The minimum detectable signal from Ex-ample 3.1 is -106 dBm or -87 dBm at the output. The IIP3 of the LNA and mixer combination from (3.22) is µµ=+=×=Þ -311202.316 10IIP3316.2 W 1 mWIIP3 43.2 W13.6 dBm This ...

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    56 System Level Architecture and Design Considerations3.2.4  Image Signals and Image Reject FilteringAt the RF frequency, there are filters to remove out of band signals that may be picked up by the antenna. Any filter in the RF section of the radio must be wide enough to pass the ent...

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    3.2 System Level Considerations 57signal will be mixed down to IF1 at 70 MHz. Thus, fLO is adjustable between 972 MHz and 998 MHz to allow signals between 902 MHz and 928 MHz to be received. The image occurs 70 MHz above fLO. The worst case will be when the image frequency is closest to the filte...

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    58 System Level Architecture and Design Considerationswill act to reduce the signal-to-noise ratio of the desired channel and could cause an increase in bit error rate. Therefore the circuits in the radio must have a suffi-ciently high linearity so that this does not happen. Once the received ban...

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    3.2 System Level Considerations 59Solution: With nonlinearity, third-order intermodulation between the pair of blockers will cause interference directly on top of the signal. The level of this disturbance must be low enough so that the signal can still be detected. The other potential problem is ...

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    60 System Level Architecture and Design Considerationsif the oscillator also has energy at the same offset Df from the carrier, then the block-ing signal will be mixed directly to the IF frequency as illustrated in Figure 3.15.Example 3.7: Calculating Maximum Level of Synthesizer SpursFor the spe...

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    3.2 System Level Considerations 61There are a few things that can be done about DC offset. If the radio uses a modulation type where there is not much information at DC (such as an OFDM signal where the first subcarrier does not contain any information), then a blocking capacitor can be placed ri...

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    62 System Level Architecture and Design Considerationsof this distortion product must be less than -95 dBm. Using (2.66), we note that P2 - P1 = (-20 - (-95)) = 75 dB. Therefore the IIP2 must be greater than -20 dBm + 75 dB = 55 dBm. 3.2.9  Receiver Automatic Gain Control IssuesADCs re...

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    3.2 System Level Considerations 633.2.10   EVM in Transmitters Including Phase Noise, Linearity, IQ Mismatch, EVM with OFDM Waveforms, and Nonlinearity Error vector magnitude (EVM) is a very important way to measure how accurately a transmitter has reproduced the...

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    64 System Level Architecture and Design Considerations =++…22212()()()totMEVMEVMEVMEVM (3.31)One source of EVM is synthesizer phase noise. As discussed in Chapter 2, the phase noise can be integrated to give a value for the rms phase variation in radians IntPNrms. This phase variation will affe...

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    3.2 System Level Considerations 65 22iaIQ=+ (3.36)In this case the EVM will be simply: IQEVMδ= (3.37)EVM can also be caused by carrier feedthrough. Carrier feedthrough can be due to finite isolation from LO to RF and from LO to IF, and DC offset, as well as other factors. Whatever the source, an...

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    66 System Level Architecture and Design Considerationswhere N is the number of subcarriers. The above equation has been verified through extensive simulations and comparison to measured results by the authors. However, note that if the output power is close to the 1-dB compression point, this for...

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    3.2 System Level Considerations 67and y is the quantized digital output. The output is a function of the input, but it has discrete levels at equally spaced intervals D. Thus, unless the input happens to be an integer multiple of the quantizer resolution (step size) D, there will be an error in r...

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    68 System Level Architecture and Design ConsiderationsFrom sampling theory, it is known that the frequency spectrum of a sampled system repeats once every sampling frequency. Thus, the spectrum of the quantiza-tion noise in a sampled system will be centered around dc and spread out to half of the...

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    3.2 System Level Considerations 69Thus, the signal-to-noise ratio (SNR) due to quantization noise power that falls into the signal band becomes: ( )æö-D⋅ç÷=»ç÷ç÷èøç÷èø221282021æö3 2OSRSNR 10log10log2NNn (3.53)Noting that log10(x) = log10(2) × log2(x), the above expression beco...

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    70 System Level Architecture and Design ConsiderationsExample 3.9: Specifying an ADCAn ADC is required to have a SNR of 30 dB and a signal bandwidth of 20 MHz. Ignoring any out of band interferers, give as much detail as possible about the per-formance the ADC would require. Solution: First let u...

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    3.3 Antennas and the Link Between a Transmitter and a Receiver 71 λπ=2r2(4 )t t rPG GPd (3.60)where Pt is the power transmitted by the transmitting antenna, Gt is the gain of the transmitting antenna, Gr is the gain of the receiving antenna, l is the wavelength, and d is the distance separating...

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    72 System Level Architecture and Design ConsiderationsNote that F(u) is the ratio of the free space EM field strength to the actual re-ceived field strength and, 121 22()ddhd dυλ+= (3.65)Obviously real environments are far more complicated then this and a theoreti-cal formula cannot be derive...

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    3.3 Antennas and the Link Between a Transmitter and a Receiver 73of the order of 1m might be used. The reference path loss PLref(do) can either be calculated from the free space loss (3.60) or it may be measured. Example 3.10: Estimating Received Power LevelsFor a 5-GHz indoor link with transmit ...

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    7575c h a p t e r 4A Brief Review of Technology4.1  IntroductionAt the heart of RF integrated circuits are the transistors used to build them. The basic function of a transistor is to provide gain. Unfortunately, transistors are never ideal because along with gain comes nonlinearity and noise. ...

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    76 A Brief Review of Technologyat a higher voltage than the base. This bias regime is known as the forward active region. Electrons are injected from the emitter into the base region. Because the base region is narrow, most electrons are swept into the collector rather than going to the base cont...

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    4.2 Bipolar Transistor Description 77another region of operation. In saturation, VCE is typically less than a few tenths of a volt. Note that in the active region, the collector current is not constant. There is a slope to the current versus voltage curve, indicating that the collector current wi...

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    78 A Brief Review of Technology4.3 b Current DependenceFigure 4.5 shows the dependence of b on the collector current. b drops off at high currents because the electron concentration in the base-collector depletion region becomes comparable to the background dopant ion concentration, leading...

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    4.5 Small-Signal Parameters 79ure 4.1) is shown at the center. The series resistances to the base, emitter and col-lector are shown respectively by rb, rE, and rc. Also, between each pair of terminals there is some finite capacitance shown as Cbc, Cce, Cbe. This circuit can be simplified by noti...

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    80 A Brief Review of TechnologyTransconductance gm is given by: cCcmTiII qgvvkTπ=== (4.5)where IC is the dc collector current. Note that the small-signal value of gm in (4.5) is related to the large-signal behavior of (4.1) by differentiation. At a low frequency where the transistor input impeda...

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    4.6 High-Frequency Effects 81residual capacitive reactance can be resonated with a series inductor so it can be ignored). Thus input power is: 2inbbvPr= (4.11)where vb is the input rms voltage on the base. The current source has an output current equal to cmig vπ= (4.12) where the magnitude of v...

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    82 A Brief Review of TechnologyUsing this result, the Miller multiplication of Cm results in 311222cvCCkCCCCCCCCvCππππµπµπµππµæöæö=+-=++=++»ç÷ç÷èøèø (4.18)Because the output is matched, it is assumed that half the current flows into the output impedance and half the curre...

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    4.7 Noise in Bipolar Transistors 83resulted in a somewhat reduced value of 60 GHz. At 71.8 GHz, the impedance of Cp is calculated to be -j3.167W. Thus, the approximation that this impedance is much less than rb or rp is justified. Calculation of fmax results in a value of 104.7 GHz. The real part...

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    84 A Brief Review of Technology4.7.2  Shot NoiseShot noise occurs at both the base and the collector, and is due to the discrete na-ture of charge carriers as they pass a potential barrier, such as a pn junction. That is to say that even though we think about current as a continuous flow, it ...

  • Page 106

    4.8 Base Shot Noise Discussion 85 2bf1mCiKIf α= (4.24)where m is between 0.5 and 2, a is about equal to 1, and K is a process constant.The 1/f noise is dominant at low frequencies as shown in Figure 4.10. However, beyond the corner frequency (shown as 10 kHz), thermal noise dominates. The ef-fec...

  • Page 107

    86 A Brief Review of Technologyis generating noise half thermally. Note that any resistor in thermal equilibrium must generate 4kTR of noise voltage. However, a conducting pn junction is not in thermal equilibrium, and power is added, so it is allowed to break the rules.4.9  Noise Sources i...

  • Page 108

    4.11 CMOS Transistors 87only when current is reduced to half of the optimum value or when it is increased by 50% over its optimum value. Figure 4.8 also shows that junction capacitance is roughly proportional to transistor size, while base resistance is inversely propor-tional to transistor size....

  • Page 109

    88 A Brief Review of TechnologyWe will now provide a brief summary of CMOS transistors. A cross section of basic NMOS and PMOS transistors is shown in Figure 4.14. The starting material is a low resistivity p- substrate. Low resistivity, typically 10 W-cm, is used to reduce the likelihood of latc...

  • Page 110

    4.11 CMOS Transistors 89even if the source is not grounded. Triple well devices are highly desirable for RF applications because of the low transconductance of CMOS devices under even the best circumstances.4.11.1  NMOS Transistor OperationThe drain characteristic curves for an NMOS transis...

  • Page 111

    90 A Brief Review of Technologyand remains nearly independent of vDS. This means the output conductance gds is relatively low, which is advantageous for high gain in amplifiers.4.11.2  PMOS Transistor OperationThe operation of PMOS is similar to that of NMOS except that negative vGS is appl...

  • Page 112

    4.11 CMOS Transistors 91l can be used to calculate the output conductance: DSdsDSdigIdvλ== (4.28)It is well known that the square law model is too simplistic. More elaborate equations are available, for example including the effects of mobility degradation and velocity saturation effects [4] res...

  • Page 113

    92 A Brief Review of Technologythe square law model especially at low overdrive voltages. However, ultimately, it is necessary to use simulators, such as Spectre, ADS, or SPICE, to verify the curves. Recently CMOS models have become much better at predicting transis-tor performance, although ther...

  • Page 114

    4.11 CMOS Transistors 93also a significant noise contribution, especially as frequencies increase past about a tenth of fT. This noise, sometimes called induced gate noise, can be modeled as an additional current ing in Figure 4.18 and is described by 22245gsngmkTCigδω= (4.40)A typical value fo...

  • Page 115

    94 A Brief Review of Technologywould have a resistance of rsW/L. The factor of 1/3 in (4.42) comes from the distrib-uted resistance in the gate and the fact that the transistor current is flowing under all regions of the gate. The series resistance varies from 0W near the contact to rsW/L for the...

  • Page 116

    4.11 CMOS Transistors 95effective minimum gate length is 0.10 mm. For a minimum length transistor with a gate width of 20 mm, compare simple square law predictions to simulation results for current, transconductance, and noise versus bias current. Also show results for fT, fmax, and transistor no...

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    96 A Brief Review of TechnologyIn this calculation, the factor of g has been left out. Also, the omission of Cgd can be quite important as it could be as high as 30% of Cgs and this would reduce fT by the same amount. A prediction for fmax is given by (4.36). To determine num-bers we need to esti...

  • Page 118

    4.11 CMOS Transistors 97and fT occur at about 7 and 8 mA, respectively; from Figure 4.20 this requires a vGS approaching that of the power supply voltage, and thus this will not be a useful operating point when more than one transistor is connected in series between the power supply rails. This p...

  • Page 119

    98 A Brief Review of Technologygm stops increasing, the noise figure no longer falls and because g is increasing, noise figure actually starts to rise at high overdrive voltages and the shape of the curve approximately matches that of the simulation. By performing a noise summary it was determine...

  • Page 120

    4.12 Practical Considerations in Transistor Layout 99a common-mode signal and can be rejected. Symmetrical circuits also prevent un-equal signal delays again ensuring that signals are properly lined up. 4.12.3  MatchingTo achieve good matching it is important that components being matched are c...

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    100 A Brief Review of Technology4.12.4  ESD Protection and Antenna RulesTransistor performance can be affected by the need to have protection against elec-trostatic discharge or ESD. ESD can be the result of external factors such as static charge. It can also be the result of processing...

  • Page 122

    101C H A P T E R 5Impedance Matching5.1  IntroductionIn RF circuits, we very seldom start with the impedance that we would like. There-fore, we need to develop techniques for transforming an arbitrary impedance into the impedance of choice. For example, consider the RF system shown in Figure 5....

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    102 Impedance MatchingUsing the above two equations, Y2 is eliminated, leaving only L and C as unknowns: in1oYj CZj Lωω=-+ Solving the real and imaginary parts of this equation, values for C and L can be found. With some manipulation: inin22inin()()oRj L XYj CRL Xωωω--=-+- The real part of ...

  • Page 124

    5.2 Review of the Smith Chart 1035.2  Review of the Smith ChartThe reflection coefficient is a very common figure of merit used to determine how well matched two impedances are. It is related to the ratio of power transmitted to power reflected from the load. A plot of the reflection co...

  • Page 125

    104 Impedance Matchingwhere the load is equal to the characteristic impedance (in other words perfect match-ing). Real impedances lie on the real axis from 0W at G = -1 to ¥ W at G = +1. Purely reactive impedances lie on the unit circle. Thus, impedances can be directly shown, normalized to Zo. ...

  • Page 126

    5.2 Review of the Smith Chart 105In addition to the reflection coefficient there are a number of other related val-ues that can be calculated. The voltage standing wave ratio (VSWR) is defined as: + G==- Gmaxmin11xxvVSWRv (5.5)where |vx|max and |vx|min are the maximum and minimum magnitudes of th...

  • Page 127

    106 Impedance MatchingAnother value that is often calculated related to the reflection coefficient is called the return loss (RL) and it is given by: 1120 log20 log1VSWRRLVSWRæ ö+æö==ç÷ç ÷èø-Gè ø (5.6)Note if the system is perfectly matched, the RL is minus infinity and the VSWR would...

  • Page 128

    5.3 Impedance Matching 107the source driving the circuit. The output impedance must be similarly matched. It is very common to use reactive components to achieve this impedance transforma-tion because they do not absorb any power or add noise. Thus, series or parallel inductance or capacitance c...

  • Page 129

    108 Impedance MatchingSometimes matching components can be used as dc blocks (capacitors) or to provide bias currents (inductors).Some circuits may result in more reasonable component values.Personal preference. Not to be underestimated, sometimes when all paths look equal you just have to shoot ...

  • Page 130

    5.3 Impedance Matching 109series inductor. Adding a parallel capacitor moves the impedance around a constant admittance circle to point B, which places the impedance on the 50W resistance circle. Once on the unit circle, a series inductance moves the impedance along a con-stant resistance circle...

  • Page 131

    110 Impedance MatchingSolution: The small signal model and calculated matching impedances are shown in Figure 5.14. The transistor has an input impedance of 1,250W in parallel with 700 fF, which at 1 GHz is equal to Zp = 40 - j220W. Using this and the base resistance of 5W, the impedance seen by ...

  • Page 132

    5.4 Conversions Between Series and Parallel RL and RC Circuits 1115.4   Conversions Between Series and Parallel Resistor-Inductor  and Resistor-Capacitor CircuitsSeries and parallel resistor-capacitor (RC) and resistor-inductor (RL) networks are widely used basic building ...

  • Page 133

    112 Impedance MatchingThus, the inverse of the real part of this equation gives Rp: 2 2 222 21(1)sspsssC RRRQC Rωω+==+ (5.9)where Q known as the quality factor is defined as before as |ZIm|/|ZRe| where Zim is the imaginary part of Z, and ZRe is the real part of Z. This definition of Q is con-ve...

  • Page 134

    5.5 Tapped Capacitors and Inductors 113Thus, the inverse of the real part of this equation gives Req: 22112222 2 22121 22eq2222()()LLLR LLL LQRRRLLω++-+-==- (5.15)where Q2 is the quality factor of L2 and R in parallel. As long as Q2 is large, then a simplification is possible. This is equivalen...

  • Page 135

    114 Impedance Matchingwhich is just the series combination of the two inductors if the resistor is absent. The same type of analysis can be performed on network Figure 4.16(a). In this case 212eq1CCRRC+æö» ç÷èø (5.19) 1eq1211CCC-æö»+ç÷èø (5.20)5.6  The Concept of Mutual In...

  • Page 136

    5.6 The Concept of Mutual Inductance 115An equivalent model for the transformer that uses mutual inductance is shown in Figure 5.19. This model can be shown to be valid if two of the ports are con-nected together as shown in the figure by writing the equations in terms of Ip and Is, and using the...

  • Page 137

    116 Impedance MatchingWe can solve for the impedance by 2 ()VZj L MIω==+ Thus since Z = jwLeq, we can solve for Leq: eq22LLM=+ In the second case for the circuit on the right in Figure 5.20, the dots are placed in such a way that the flux is reduced. We repeat the analysis: 2Vj LI j MIωω=- 2...

  • Page 138

    5.8 Tuning a Transformer 117Note that here we have defined N as the inductance ratio, but traditionally it is defined as a turns ratio. Since in an integrated circuit turns and inductance are not so easily related, this alternative definition is used. Now if the secondary is loaded with impedance...

  • Page 139

    118 Impedance MatchingTaking the imaginary part of this expression, the inductance seen looking into the primary Leff can be found, making use of (5.21) to express the results in terms of the coupling coefficient k: ωω--+=-+2 22 22eff2 222(1)(1)s ppLpsLL LkR LLLkR (5.27)When k = 1, or when k = ...

  • Page 140

    5.9 The Bandwidth of an Impedance Transformation Network 119In general, this second-order transfer function has the form: 22( )ooA sA sssBWω=++ (5.31)where =1BWRC (5.32)and 1oLCω = (5.33)This is an example of a damped second-order system with poles in the left-hand half plane as shown in Fig...

  • Page 141

    120 Impedance Matchingfrequency at which the gain of the transfer function is down by 3 dB relative to the gain at the center frequency. 5.10  Quality Factor of an LC ResonatorThe quality factor, Q, of an LC resonator is another figure of merit used. It is de-fined as Stored / CycleLo...

  • Page 142

    5.10 Quality Factor of an LC Resonator 121Solution: The matching circuit will look much like that shown in Figure 5.25. We will use the secondary of the transformer as a resonant circuit so that there will be no reactance at 2 GHz. We first add capacitance in parallel with the input capacitance s...

  • Page 143

    122 Impedance MatchingA comparison of frequency response (Figure 5.28) clearly shows the bandwidth broadening effect of matching in two steps. To quantify the effect, the magnitude of the input impedance is shown in Figure 5.29.5.11  Broadband Impedance Matching In many cases it may be ne...

  • Page 144

    5.11 Broadband Impedance Matching 123 ωωωω====1,322311sHH ssLL sRLCRRLCR (5.39) where wH and wL are the upper and lower frequencies over which the circuit is to be matched. Note that the circuit in Figure 5.30 is shown with three stages; how-Figure 5.28  Frequency response for one-step an...

  • Page 145

    124 Impedance Matchingever, an arbitrary number of ladder stages may be used in theory. More stages can cause additional loss if the components are less than ideal, but will have the added advantage that any process tolerance causing a change in any one value will have a lesser impact on the over...

  • Page 146

    5.12 Transmission Lines 1255.12  Transmission Lines When designing circuits on-chip, often transmission line effects can be ignored, but at chip boundaries they are very important. Transmission lines have effects that must be considered at these interfaces in order to match the input or ou...

  • Page 147

    126 Impedance Matchingthe impedance looking into the transmission line is periodic with distance. It can be shown from (5.40) that for each distance l traveled down the transmission line, the impedance makes two clockwise rotations about the center of the Smith chart. Transmission lines can also ...

  • Page 148

    S11 is the input reflection coefficient, measured with the output terminated with Zo. This means the output is matched and all power is transmitted into the load; thus a2 is zero. 222110abSa== (5.45)S21, the forward transmission coefficient, is also measured with the output ter-minated with Zo. S...

  • Page 149

    128 Impedance Matchingparameters, which can be used with the well-known microwave techniques to find maximum gain, optimal noise figure, stability, and so forth. However, the simula-tors, which use the models to generate the S-parameters, can be used directly to find maximum gain, optimal noise f...

  • Page 150

    [6] Ismail, A., and A. Abidi, “A 3–10-GHz Low-Noise Amplifier with Wideband LC-Ladder Matching Network,” IEEE J. Solid-State Circuits, Vol. 39, December 2004, pp. 2269–2277. [7] Bevilacqua, A., and A. Niknejad, “An Ultrawideband CMOS Low-Noise Amplifier for 3.1–10.6-GHz Wireless Re...

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    c h a p t e r 6the Use and Design of passive circuit elements in Ic technologies6.1 IntroductionIn this chapter, passive circuit elements will be discussed. First, metalization and back-end processing (away from the silicon) in integrated circuits will be described. this is the starting point for...

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    LRWtρ=sWRtLρρæö= = ç÷èøfρδπ µ=

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    W×===W×ρµµµµ3cm 100 m50 m20 m 3 mLRWt-W===×××ρµδµπ µππ723cm1.23 m5 GHz 4 10NfAW×===W---×-×ρµµδδµµµµ3cm 100 m59.3 m(2 )(2 )20 m 3 m 17.5 m 0.54 mLRWtWt

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    o r AChε ε=11420.77 1.061.06o rWWtChhhε εéùæöæ öêú=+++ç÷ç ÷èøè øêúëû

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    =+=+=µµµavgoutin11()(270 m 161 m) 215.5 m22dDD--===++outinoutin() (270 m 161 m)0.253() (270 m 161 m)DDDD

  • Page 167

    -×==××=+×22avg723 215.5 m2.342.34 4 103.36 nH1 + 2.751 2.75 0.253on dNLA-×××××===2122oxide8.85 103.9 2.3 mm 20 mm317.6 fF5 mo rCANCd-×××××===2122underpass8.85 103.9 76 m 20 mm17.4 fF3 mo rCANCd-×××-××===2122IW8.85 103.9 (2.3 mm 0.62 mm) 3 mm58 fF3 mo rCANCdW×===W×DC3 m cm 2.3...

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  • Page 192

    171C H A P T E R 7LNA Design7.1  Introduction and Basic AmplifiersThe LNA is the first block in most receiver front ends. Its job is to amplify the signal while introducing a minimum amount of noise to the signal.Gain can be provided by a single transistor. Since a transistor has three te...

  • Page 193

    172 LNA DesignThe input impedance of the circuit at low frequencies is given by: inbZrr= + (7.2)In the case of a CMOS transistor, the low frequency input impedance would be given by: in1ggsZrsC=+ (7.3)which will approach an open circuit at low frequency.However, at RF, Cp will provide a low imp...

  • Page 194

    7.1 Introduction and Basic Amplifiers 173 1(1)Am Lm LCCCg ZC g Zæö==+»ç÷èøvv (7.4) 111Bm LCCCCg Zæöæö==+»ç÷ç÷èøèøvv (7.5)There are now two equivalent capacitors in the circuit: one consisting of CA + Cp and the other consisting of CB. This means that there are now two RC time...

  • Page 195

    174 LNA Designthe current gain reduces by 3 dB is given by: 12()fr CC=×+ (7.9)The unity current gain frequency can be found by noting that with a first-order roll-off, the ratio of fT to fβ is equal to the low-frequency current gain β. The result-ing expression for fT is: 2 ()mgfCC=×+ (7.10)F...

  • Page 196

    7.1 Introduction and Basic Amplifiers 175Example 7.3: Calculation of Gain of Single Pole AmplifierFor the above example, for Avo = 20 with fP1 = 2.76 GHz, calculate the gain at 5.6 GHz.Solution:With fP1 = 2.76 GHz, at 5.6 GHz, the gain can be calculated to be 8.84, or 18.9 dB. This is down by abo...

  • Page 197

    176 LNA Designand 1cPb» - (7.16) 2Pb» - (7.17)Example 7.5: Calculation of Poles and Zeros with Simplified ExpressionsWith the expression as above, the poles occur at 2.60 GHz and 120.94 GHz, which are reasonably close to the exact values.7.1.3  The Common-Base/Gate Amplifier (Cascode)Th...

  • Page 198

    7.1 Introduction and Basic Amplifiers 177case, the current ic1 through Q1 is about the same as the current iC2 through Q2 since the common-base amplifier has a current gain of approximately 1. Then, ic1 » ic2 = gm1vi. For the case where RS + rb << rp , and vo /vi » -gmRC, the gain is th...

  • Page 199

    178 LNA DesignAnother advantage of the cascode amplifier is that adding another transistor improves the isolation between the two ports (very little reverse gain in the am-plifier). The disadvantage is that the additional transistor adds additional poles to the system. This can become a problem f...

  • Page 200

    7.1 Introduction and Basic Amplifiers 179Avo is the gain at low frequency and is given by: ππ+=»=»+++++/11()/11/m EEm EEvom EBEm EmEg RR rg RRARRRrg RgRg (7.21)where RB = RS + rb. The first approximation in (7.21) is valid only if rp >> RB + RE and this is always true for CMOS and can b...

  • Page 201

    180 LNA DesignAt low frequencies, this further simplifies to: out1emZrg» » (7.30)At higher frequencies if re > RB, (recalling that RB = RS + rb), for example, at low current levels, then |Zout| decreases with frequency and so the output impedance is capacitive. However, if re < RB, then |...

  • Page 202

    7.2 Amplifiers with Feedback 181Solution:Solving for the various components, it can be shown that low-frequency output resistance is 5.5W and high-frequency output impedance is 55W. The equivalent inductance is 0.2 nH, the zero frequency is 4.59 GHz, and the pole frequency is 45.9 GHz.7.2  Ampl...

  • Page 203

    182 LNA DesignThe gain of any of these amplifiers at the resonance frequency of the collector or drain tank, ignoring the effect of Cm for the bipolar circuits or Cgd for the CMOS circuits is found with the aid of Figure 7.9 and is given by: 1om LLiEEm EVg RRVZZg ZZπ-=» -æö++ç÷èø (7.35)wh...

  • Page 204

    7.2 Amplifiers with Feedback 183where ωo is the frequency of interest. Note that nodal analysis will not result in the same expression unless the input impedance is set equal to RS and in practice this requires the addition of an input inductor. The input impedance has the same form as the commo...

  • Page 205

    184 LNA DesignThe input impedance of this stage is also changed dramatically by the presence of feedback. Ignoring Cm or Cgd for a CMOS amplifier, the input admittance can be computed to be: in11Lm LfffLRg RRYRRRZπ-=+++ (7.41)Alternatively, the input impedance can be given by: in()(1)fLfLfLffLm ...

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    7.2 Amplifiers with Feedback 185does change the previously developed formulas somewhat. With the addition of a buffer, the voltage gain is no longer affected by the feedback so it is approximately that of a common emitter amplifier given by (RL/(RE + 1/gm)) minus the loss in the buffer. However, ...

  • Page 207

    186 LNA Design(Note the exact expression from the same equation would have resulted in 16.5, so the approximate expression is sufficient.) Thus, the gain has been reduced from 26 dB to 24.4 dB. From the source, the gain is reduced much more since the input impedance is much reduced so there is a ...

  • Page 208

    7.3 Noise in Amplifiers 187When the input is shorted in Figure 7.12(b), vn is the only source of noise in the model, and assuming that rb is small enough to have no effect on the gain, the output noise current ion_tot would be: 222on_totnmiv g= (7.45)If instead the actual noise sources in the mod...

  • Page 209

    188 LNA Designwhere ==224and2bnbcncvkTriqI . Now if the input is open circuited in Figure 7.12(b), then only in can have any effect on the circuit. In this case the output noise is: 2222on_totnmii Z gπ= (7.48)Similarly for the model in Figure 7.12(a): π=+22222on_totbnmcniiZ gi (7.49)Now solving...

  • Page 210

    7.3 Noise in Amplifiers 189where it is assumed that rp is not significant. Explicitly: 0cG» (7.56) cBCπω= (7.57)Thus, the correlation admittance is just equal to the input impedance of the transistor.Rc, Ru, and Gu can also be written down directly. ====22214224cCTcCmmvqIvRkTIgkTg (7.58) 2444u...

  • Page 211

    190 LNA Designwe will see how to set the actual input impedance so that it is also equal to 50W, making it feasible to match both power and noise simultaneously. The expression for Bopt can be simplified if rb is small compared to 1/2gm. This would be a reasonable approximation over most normal o...

  • Page 212

    7.3 Noise in Amplifiers 191will be shown in the CMOS design example; however, it can be noted that the results are not that different. It can also be noted that in practice at low gigahertz frequencies, the gate induced noise term, the last term in (7.66), can often be left out to simplify the ca...

  • Page 213

    192 LNA DesignAlso, the imaginary part of the input impedance must equal zero. Therefore: 21sbmR CLgCππω=- (7.70)Making use of the above analysis, as well as the discussions on noise so far, the following method for simultaneously matching an LNA for power and noise was created. It is outlined...

  • Page 214

    7.3 Noise in Amplifiers 193example design, a simple buffer so that the circuit can drive 50W. Assume that a 50-GHz, 0.5-mm SiGe technology is available. Solution:At 1.8V it is still possible to design an LNA using a cascode configuration. The cas-code transistor can have its base tied to the supp...

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    194 LNA Designan fT of about 34 GHz. Using the equation for fT, and noting that at 1 mA, gm is 0.04A / V, an estimate for Cp is 0.04187fF234mTgCGπωπ»==´ Also noting that the 15´ transistor in Chapter 4 had an rb of 5W, gmrb is equal to 0.2, Gopt can be estimated from (7.63)2222opt222()0.042...

  • Page 216

    7.3 Noise in Amplifiers 195of 4.6 mA, very nearly the same as the predicted results. Now the transistor size and current are determined. From a dc simulation the Cp of the transistor may be found and in this case was 742.5 fF. Since the current is 4.6 mA, the gm is 184 mA / V and thus the fT is 3...

  • Page 217

    196 LNA Designperfectly matched at 5 GHz as designed. Of course in practice, loss from inductors as well as packaging and bond wires would never allow such perfect results in the lab. The gain is plotted in Figure 7.19. Note that it peaks about 400 MHz lower than initially calculated. This is due...

  • Page 218

    7.3 Noise in Amplifiers 197achievable noise figure of 1.74 dB (F = 1.49) showing that we have, in fact, a noise match for the circuit at 5 GHz. A calculation can be done for noise to compare to simulated values using (7.62) βæö= ++++ç÷èø= ++++=®2112221 0.058 0.054 0.074 0.022 1.2080.82 dB...

  • Page 219

    198 LNA Designin-chip components, it may be possible to operate with much higher output imped-ance and hence much lower current.Initially, we start with the same transistor characterized in Chapter 4, with a 20-micron gate width. Its minimum noise figure NFmin versus transistor bias cur-rent is s...

  • Page 220

    7.3 Noise in Amplifiers 199seen from Figure 7.22(a), for a 200-mm transistor, there is very little noise penalty for decreasing the current down to about 2 mA, so this value was selected. At 2 mA, the transistor has a gm of about 40 mA / V, an input Cgs of about 230 fF, and an fT of about 28 GHz...

  • Page 221

    200 LNA DesignThe gain to the drain can be predicted from (7.38). The output source follower further reduces the gain according to its output impedance, approximately equal to 1/gm of the output transistor. The buffer current was adjusted to result in ap-proximately 50W output impedance, although...

  • Page 222

    7.3 Noise in Amplifiers 201Since the transistors are operated at very low current densities, the long chan-nel approximations are used for g and d, as discussed in Chapter 4, that is, g = 0.67 and d = 1.33.It can be noted that the above equation for the noise factor is valid for a common- source ...

  • Page 223

    202 LNA DesignNote that this noise voltage is proportional to the collector current, as is the signal, so the SNR is independent of bias current. The collector shot noise is in parallel with the collector signal current and is directly sent to the output load resistor. ,2cno IC LvqI R» (7.72)Not...

  • Page 224

    7.3 Noise in Amplifiers 203similar to the bipolar case. Finally, the gate induced noise power is inversely pro-portional to gm, δωα»´2222,45ggsmLno ikTCvgRI (7.77)hence, the noise figure will also improve with the increasing current, unlike the noise figure due to the base shot noise in a b...

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    204 LNA Design7.3.7  Noise in the Common-Collector/Drain AmplifierSince this type of amplifier is not often used as an LNA stage, but more commonly as a buffer, we will deal with its noise only briefly. The amplifier with noise sources is shown in Figure 7.27. Noise due to rb is directl...

  • Page 226

    7.4 Linearity in Amplifiers 2057.4  Linearity in AmplifiersNonlinearity analysis will follow the same basic principles as discussed in Chapter 2, with power series expansions and nonlinear terms present in the amplifier. These will now be discussed in detail.7.4.1  Exponential Nonlinea...

  • Page 227

    206 LNA DesignNow making use of the math identity: 2311ln(1)23xxxx+= -+… (7.86)and expanding (7.85) using (7.86) and substituting it back into (7.83), we get: 231123cccsE cTCCCiiivR ivIIIéùæöæöêú=+-+ç÷ç÷èøèøêúëû… (7.87)Noting that vT /IC = re and rearranging, we get: 23211...

  • Page 228

    7.4 Linearity in Amplifiers 207Now the third-order intercept voltage can be determined (note that this is the peak voltage and the rms voltage will be lower by a factor of 2): ()+æö+===ç÷+-èø-5221IP333611222 23322CEeEeTEeeEeeEeIRrRrkvvkRrr RrrRr (7.94)This very useful equation can be used t...

  • Page 229

    208 LNA Design 23231230.040.810.667cssssssik vk vk vvvv=+++=+++…… The dc component, fundamental, second harmonic, intermodulation compo-nents, and equations are listed for the above coefficients in Table 7.1.The intercept point is at a voltage of 70.7 mV at the input and 2.828 mA at the outpu...

  • Page 230

    7.4 Linearity in Amplifiers 209Thus, the waveform is centered on 5 mA.Because of positive coefficient k3, the waveform is not compressed, but ex-panded. However, either way, compression or expansion, the result is distortion.The above calculations all assume that RC is small enough so that the tr...

  • Page 231

    210 LNA Designillustrated in Figure 7.29. Instead, for this example, values for k0, k1, k2, k3 are determined from the equations in Table 7.1. Then these are used to calculate the fundamental and third-order intermodulation (IM3) components from the equa-tions in Table 7.1 and IIP3 calculated fro...

  • Page 232

    7.4 Linearity in Amplifiers 211conditions, k3 can be set to zero for improvements in linearity [4]. In MOSFETs, it turns out to be quite challenging to take advantage of this linearity improvement, since the peak occurs for a narrow region of bias conditions and the use of degen-eration resistanc...

  • Page 233

    212 LNA Designwhere VA is the Early voltage of the transistors. An ac current into the collector can be written as a function of ac current ic. _ ac( )AocCcVriIi=+ (7.99)Assuming for this analysis, that there is no other significant impedance in the circuit other than the transistor output resist...

  • Page 234

    7.4 Linearity in Amplifiers 213the designer has two choices if the current source is not linear enough. They can ei-ther increase the current or increase the output impedance. Also, it should be noted that this relationship only holds true if the transistor does not start to saturate. If it does,...

  • Page 235

    214 LNA DesignIf Rout is large enough that iout is always much less than IB, the linearity will be good, as the operating point will not change significantly over a cycle of the sig-nal. It is important to keep the peak output current less than the bias current. This means that: ,peakout||oBvIR&l...

  • Page 236

    7.6 Differential Amplifiers 215load impedance is not fully known for all frequencies, and hence making the circuit unconditionally stable would be recommended. For example, for a power ampli-fier or LNA connected to a 50W antenna, it can happen that a potential stability problem is identified awa...

  • Page 237

    216 LNA Designin Figure 7.35. Here the bias for the stage is supplied with a current source in the emitter. Note that when the bias is applied this way, the emitter is at a vir-tual ground. This means that for small-signal differential inputs, this voltage never moves from its nominal voltage.Thi...

  • Page 238

    7.6 Differential Amplifiers 217intersects the axis at vL given by the ratio of the nominal bias current IC (equal to IEE/2) to the effective transconductance gmeff (equal to IEE/4vT), or ====»22250 mVCEETLEETmeffmEEIIvvIvggI (7.115)7.6.2  Linearity in Bipolar Differential PairsAs show...

  • Page 239

    218 LNA Design7.6.3  CMOS Differential PairThe transfer characteristics of a CMOS differential pair, shown in Figure 7.36, can also be determined using the simple square law model for the transistor.Given that 1GS1GS2vvv=- (7.122)We can solve for v1 as function and of iD1 and iD2 using the ...

  • Page 240

    7.6 Differential Amplifiers 219where the variable K gathers the process constants and transistor size as oxWKCLµæö=ç÷èø (7.128)7.6.4  Linearity of the CMOS Differential PairThe equation for current can be expressed as a power series by using the binomial expansion: 1/ 22311(1)...

  • Page 241

    220 LNA DesignIt can be noted that the factor of 3.226 is equivalent to 10.3 dB. This is close to the 9.66 dB that vIP3 is higher than the 1-dB compression voltage v1dB; thus, vL is approximately equal to v1dB. Note that these voltages are all peak differential. Thus, the linearity of a CMOS diff...

  • Page 242

    7.7 Low Voltage Topologies for LNAs and the Use of On-Chip Transformers 221An alternative to this topology involves using a transformer to produce mag-netic, rather than electric, coupling between the two stages, as shown in Figure 7.37(b). In this circuit, Lp and Ls form the primary and seconda...

  • Page 243

    222 LNA DesignFigure 7.39  Redrawn transformer-coupled LNA.is increased by a factor of n, the current is decreased by a factor of n. However, in this circuit, the transistor feeds the primary current into the secondary adding it to the secondary current, but also allowing a lower impedance to...

  • Page 244

    7.8 DC Bias Networks 223circuit to reduce the gain of the transistor, as shown in Figure 7.40(b). If Q1 is going to drive many current stages, then base current can affect the matching, so an ad-ditional transistor can be added to provide the base current without affecting Ibias, as shown in Figu...

  • Page 245

    224 LNA Design =D» -D�constant2 mV/ CcBEivT (7.140) 0.5%/ CTβD » +D� (7.141)A typical temperature range might be 0° to 85°C. Thus for a constant voltage bias, if the current is 1 mA at 20°C, then (7.139) predicts it will change to about 0.2 mA at 0°C and about 71 mA at 85°C, taking in...

  • Page 246

    7.8 DC Bias Networks 225 -×-×æö=+++ç÷èø2.32.3lnlnBEBEOBGOCOCOdVVVkTk kIdTTqTqqI (7.144)Note that this expression shows that not a lot can be done to adjust the slope of the temperature dependence. Next, to cancel this negative temperature/voltage relationship, a voltage that increases wit...

  • Page 247

    226 LNA Design ==+ref121BEBERVVVV (7.147)where VR1 is the voltage drop across the resistor R1. Therefore, the voltage across the resistor R1 can also be given by: =-112RBEBEVVV (7.148)Since this voltage is proportional to the difference of two base emitter voltages, Vref is the sum of two voltage...

  • Page 248

    7.8 DC Bias Networks 227through resistor R1, which is a PTAT current and the current flowing through R2. The voltage across R2 is equal to VBE1; thus, the current Iref is given by: -=+121ref12BEBEBEVVVIRR (7.150)Since Iref is made up of one component that is proportional to temperature and one th...

  • Page 249

    228 LNA Designover temperature. An even more extreme slope to the current temperature curve may be required in practice. In this case it is possible to make a reference current that is the difference of either a constant gm current and a ZTC current or the dif-ference between a PTAT and a ZTC cur...

  • Page 250

    7.9 Broadband LNA Design Example 229The total current must be divided between the two stages of this amplifier. The buffer must have enough current so that it continues to operate properly even when it has to deliver a lot of current in the presence of large signals. Since the load resis-tance is...

  • Page 251

    230 LNA DesignThe noise figure of this design can now be estimated. First, the noise voltage produced by the source resistance is: -==× ×× W =21ns44 (4 10) 751.1 nV / HzsvkTR Since the input is matched, this voltage is divided by half to the input of the driver transistor and then sees the ful...

  • Page 252

    7.10 Distributed Amplifiers 231very constant. The magnitude of S11 is shown in Figure 7.46 and is less than –19 dB over the whole range. Thus, the circuit is almost perfectly matched to 75W over all frequencies. The noise figure was also simulated and is shown in Figure 7.47. The noise figure w...

  • Page 253

    232 LNA DesignTransmission lines can have flat response to very high frequency in spite of parasitic components, if the line is terminated in its characteristic impedance. Such parasitic components consist of inductance in series and capacitance in parallel. If the line is modeled with a discrete...

  • Page 254

    7.10 Distributed Amplifiers 233in additional power dissipation and noise. If the lines are ac coupled to allow the amplifiers to be locally biased, the lower frequency cutoff is determined by the size of the coupling capacitors. A brief design procedure for the distributed amplifier will be given...

  • Page 255

    234 LNA Designparticular line, the ratio remains the same. That is, for N times as many sections, both L and C are reduced to 1/N and the ratio remains the same. The cutoff frequency of the transmission line is given by 11cfLCπ= (7.153)Thus, by breaking the line into more sections, as both L and...

  • Page 256

    7.10 Distributed Amplifiers 235For two or five stages, L and C are simply divided by 2 and by 5, respectively, for which the resulting cutoff frequency will go up by a factor of 2 and 5 to 96.6 GHz and 241.5 GHz, respectively. The resulting schematics were simulated, with results shown in Figure...

  • Page 257

    236 LNA Designfrequency is approximately equal to or greater than the maximum operating frequency. Note that the maximum useful frequency is about 45% of fc for k sections and about 85% of fc for m-derived sections. Note that fmax is the upper limit for the maximum operating frequency.The line ca...

  • Page 258

    7.10 Distributed Amplifiers 237 [7] Long, J. R., and M. A. Copeland, “A 1.9GHz Low-Voltage Silicon Bipolar Receiver Front-End for Wireless Personal Communications Systems,” IEEE J. Solid-State Circuits, Vol. 30, December 1995, pp. 1438–1448. [8] Cassan, D. J., and J. R. Long, “A 1-V Trans...

  • Page 259

    238 LNA DesignRudell, J. C., et al., “A 1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Applications,” IEEE J. Solid-State Circuits, Vol. 32, December 1997, pp. 2071–2088.Samavati, H., H. R. Rategh, and T. H. Lee, “A 5-GHz CMOS Wireless LAN Receiver Front End,...

  • Page 260

    239C h a p t e r 8Mixers8.1  IntroductionThe purpose of the mixer is to convert a signal from one frequency to another. In a receiver, this conversion is from radio frequency to an intermediate frequency, or to baseband for a direct conversion receiver. In a transmitter, this conversion is from...

  • Page 261

    240MixersFigure 8.1. The input of the mixer is simply a gain stage like one that has already been considered. The amplified current from the gain stage is then passed into the switching stage. This stage steers the current to one side of the output or the other depending on the value of v2 (this ...

  • Page 262

    8.4 Transconductance-ControlledMixer241Thus, the difference in the output currents from the mixer is given by 22212//11tanh211TTooov vv vTviiiIIvee-æö= - =-=ç÷èø++ (8.2)This can be converted to a differential voltage with equal load resistors in the collectors.Now, if we assume the current ...

  • Page 263

    242MixersFor a CMOS differential pair, from Chapter 7, the currents are: ()oxo221,22o1224mDCIg vWivILµæö=±-ç÷èø (8.4)where oomoxWgCIKILµ== (8.5)where K gathers the process constants and transistor size as oxWKCLµæö=ç÷èø (8.6)Thus, the difference in the output currents from the mix...

  • Page 264

    8.5 Double-BalancedMixer243This removes the v2 feedthrough term that was present in (8.3).The last step to making this circuit practical is to replace the ideal current sources with an actual amplifier stage, as shown in Figure 8.5. Now v1 is applied to a differential pair so that the small-signa...

  • Page 265

    244Mixersand 1212oeEviIrR=-+ (8.13)Currents from the switching quad are related to v2, i1, and i2 by (8.2) through (8.11). --=+=+=+=+222213/14/25/26/1111TTTTv vv vv vv viieiieiieiie (8.14)Then, assuming that the amplifier formed by Q1 and Q2 is linear, 221354612() () tanh() tanh22TTeEvvviiiiiivvr...

  • Page 266

    8.6 MixerwithSwitchingofUpperQuad2458.6  Mixer with Switching of Upper QuadUsually a downconverting mixer is operated with v1 as the RF signal and v2 as the local oscillator. The RF input must be linear, and linearity is usually improved by degeneration resistors in the case of bipola...

  • Page 267

    246MixersThis is equivalent to alternately multiplying the signal by 1 and -1. For the CMOS mixer, this becomes 21( )IFmDRFvu v g Rv= (8.21)If the CMOS mixer had degeneration resistors RE, the equation would be 21( )1/IFDRFmEvRu vvgR=+ (8.22)Note that it is assumed that the current to voltage rel...

  • Page 268

    8.6 MixerwithSwitchingofUpperQuad247larger than about 0 dBm, there is minimal further improvement. Thus, -10 to 0 dBm (100–300 mV) is a reasonable compromise between noise figure, gain, and required LO power. If the LO voltage is made too large, then a lot of current has to be moved into and ou...

  • Page 269

    248Mixers8.6.3  Analysis of Switching ModulatorThe top switching quad alternately switches the polarity of the output signal as shown in Figure 8.8.The LO signal has the effect of multiplying the RF input by a square wave going from -1 to +1. In the frequency domain, this is equivalent to...

  • Page 270

    8.6 MixerwithSwitchingofUpperQuad249change of -3.9 dB. Third harmonic terms are down by 1/3 or -9.5 dB, while fifth harmonics are 1/5 or -14 dB. Intermodulation (other than mixing between RF and LO) is often due to the RF input and its nonlinearity. Thus, the analysis of the dif-ferential pair ma...

  • Page 271

    250MixersNote also that any signals close to the LO or its multiples can mix into the IF. These signals can be other signals at the input, intermodulation between input signals (this tells us we need linear RF inputs), noise in the inputs, or noise in the mixer itself.8.7  Mixer NoiseMixer no...

  • Page 272

    8.7 MixerNoise251noise sources in the circuit get translated to different frequencies and this often “folds” noise into the output frequency. Generally, mixers have three frequency bands where noise is important: Noise already present at the IF: The transistors and resistors in the circuit wi...

  • Page 273

    252Mixersvoltages, the signal-to-noise ratio is very poor, so time spent in this region should be minimized.In order to determine noise figure, the relative value of the total noise compared to the noise from the source must be determined. Very conveniently, the calculated noise figure is approxi...

  • Page 274

    8.7 MixerNoise253Example8.2:MixerNoiseandGainwithDegenerationIn this example for a mixer as in Figure 8.13, some equations and simulation results will be shown for noise and gain versus degeneration.Without consideration of input and output matching, the noise sources as-sociated with RS and RE b...

  • Page 275

    254Mixerswhere vno,RE and vno,RS are the output noise due to RS and RE and vn,RE and vn,RS are the noise voltage associated with each resistor. Thus, with degeneration, gain will decrease unless RC is increased to match the increase of RE. Similarly, the noise figure will degrade with increasing ...

  • Page 276

    8.7 MixerNoise255The final row in Table 8.1 shows for each specified input frequency, the total number of equivalent frequency bands that have approximately the same noise. For example, for every noise input at the RF frequency, there is an approximately equal input at the image frequency. Thus, ...

  • Page 277

    256Mixersthe RF (and image frequency). For the load resistor, the only important component occurs at the IF, while for the quad switching transistors, both the RF and the IF are important. Generally, noise around the LO second harmonic or higher harmonics is not important; however, the third harm...

  • Page 278

    8.7 MixerNoise257tive to RS. If RB is comparable to RS, then a voltage divider would have to be added to the equation. The extra factors of 1 and 2 in this and the following equations indicate the number of sources (in this case a single source resistance with thermal noise) and the number of ban...

  • Page 279

    258MixersAs a reminder, as indicated above, for this equation, it is assumed that there are two each of RC, RL, and RE, and it is assumed that both RC and RL contribute to the noise. This equation is for double-sideband noise figure. For single-sideband noise factor, input noise in the denominato...

  • Page 280

    8.8 Linearity259noise. This equation is for double-sideband noise figure. For single-sideband noise factor, input noise in the denominator of (8.46) would be assumed to be due only to the noise in the RF band; thus, single-sideband noise factor would be 3 dB higher than double-sideband noise fact...

  • Page 281

    260MixersIP3 is related to vL the linear extrapolation of the axis of the transfer curve. The resulting expression is 342IPTLvvv== (8.47)As discussed in Chapter 7, for small values of degeneration resistor, the same value of 2vL is used to estimate linearity resulting in the following ==+=+32422(...

  • Page 282

    8.8 Linearity261With nonlinearity in the RF input stage, the currents i1 and i2 are composed of a large number of frequency components. Each of these frequencies is then mixed with each of the LO harmonics, producing the IF output. Many of the IF frequen-cies (such as mixing of harmonics of the r...

  • Page 283

    262MixersIf the output needs to drive a low impedance such as 50W, often an emitter fol-lower is used at the output. This can be a fairly broadband circuit, since no tuned components need be used, but could cause some distortion.8.9  Improving IsolationIt is also possible to place an inductor...

  • Page 284

    8.10 GeneralDesignComments2638.10.1  Sizing TransistorsThe differential pair that usually forms the bottom of a double-balanced mixer is basically an LNA stage, except that the transistors are usually optimized first for linearity and gain, then for noise. The switching quad transistors are t...

  • Page 285

    264MixersIf the compression is due to the bottom differential pair (RF input), then in a bipolar mixer, or in a CMOS mixer with degeneration, linearity can be im-proved by increasing RE or by increasing bias current. We note from (8.51) that increased RE will result in decreased gain. Increased b...

  • Page 286

    8.10 GeneralDesignComments265has a strong influence on the gain and noise. For a differential circuit, such as the mixer, the ground is a virtual ground and the connection to the external ground is typically through a current source. Thus, the bond pad on the ground node here has minimal impact o...

  • Page 287

    266Mixerscan be used to achieve the desired linearity, then scaling is done to achieve the de-sired gm, for example to achieve the desired gain and noise figure.Linearity requires not only that the input differential pair has the appropriate linearity as given by the above plots, but that the bia...

  • Page 288

    8.10 GeneralDesignComments2670.41V would result in a bias current of 0.2 mA through each transistor in the RF stage, which means Io is 0.4 mA. For this low level, a VDS of 0.2V is adequate. Bias voltages are shown in Figure 8.24. This leaves a significant amount of head room for the output signal...

  • Page 289

    268Mixersdown by a factor of 0.4 and final noise factor will be 7 for a noise figure of about 8.5 dB, leaving some margin for additional sources of noise. The resulting transistor size is 50 mm, and the bias current is 0.5 mA per side for a total of 1 mA.The initial design is now complete and sim...

  • Page 290

    8.11 Image-RejectandSingle-SidebandMixer269been plotted in millivolts, and RF input and IF output voltages have been shown. IP3 referred to the available power from the RF port is at about –7.1 dBm. Using markers on the original RF input plot (not shown), this corresponds to a voltage level of ...

  • Page 291

    270MixersAs can be shown, the use of the phase shifters and mixers will cause one sideband to add in phase and the other to add in antiphase, leaving only the desired side-band at the output. Which sideband is rejected depends on the placement of the phase shifts or the polarity of the summing bl...

  • Page 292

    8.11 Image-RejectandSingle-SidebandMixer2718.11.2  Generating 90° Phase ShiftSeveral circuits can be used to generate the phase shifts as required for single-side-band or image-reject mixers. Some of the simplest are the RC circuits shown in Figure 8.32. The transfer functions for the tw...

  • Page 293

    272Mixersa real circuit, the amplitude or phase may be shifted from their ideal value. Such mismatch between the amplitude or phase can come from a variety of sources. For example, R and C can be poorly matched, and the time constant could be off by a large percentage. As shown in Figure 8.32, su...

  • Page 294

    8.11 Image-RejectandSingle-SidebandMixer273put of the differential amplifier. It may also be necessary to buffer the phase shift output.This circuit is sometimes known as a first-order polyphase filter. The polyphase filter will be discussed in the next section.PolyphaseFiltersA multistage polyph...

  • Page 295

    274Mixersdriven. The inputs can be driven with four-phases, or simple differential inputs can be applied at nodes a and c. With the simple differential inputs, the other nodes, nodes b and d can be connected to a and c, left open or grounded.The polyphase filter is designed such that at a particu...

  • Page 296

    8.11 Image-RejectandSingle-SidebandMixer2752. Now V1 experiences an amplitude error relative to V2 and V2 experiences a phase shift that is not exactly 90° to give V3 and V4, respectively. 3LORFIMLO11(1)cos()(1)cos()22VAtAtωωωω=+ D-++ D- (8.57) 4LORF12IMLO1211cos[()+]cos[()]22Vttεεεεω...

  • Page 297

    276Mixersfor 20 dB of image rejection, but more like 2% is required for 40 dB of image rejec-tion. Likewise, phase mismatch must be held to less than 1.2° for 40 dB of image rejection, phase mismatch of less than 11.4° can be tolerated for 20 dB of image rejection.8.12  Alternative Mixer ...

  • Page 298

    8.12 AlternativeMixerDesigns277mixers which make use of inductors and transformers, and some other low voltage mixers.8.12.1  The Moore MixerIn a receiver, the noise produced by the mixer is sometimes very important. If the mixer is to use resistive degeneration and it is to have its phase ...

  • Page 299

    278MixersTo achieve matching, the same conditions as for an LNA are required, starting with: 02ETZLfπ= (8.67)The resulting linearity is approximately given by: 0IIP32mTg Zfωπ» (8.68)Figure 8.38  Mixerwithtransformerinput.Figure 8.39  Mixerwithsimultaneousnoiseandpowermatch.

  • Page 300

    8.12 AlternativeMixerDesigns279Noise matching is achieved by sizing LE, selecting transistor size, and operat-ing the RF transistors at the current required for minimum noise figure. The quad switching transistors are sized for maximum fT, which typically means they will end up being about 5 to 1...

  • Page 301

    280Mixers8.12.5  CMOS Mixer with Current ReuseAn opportunity with CMOS is to replace an NMOS differential pair with a PMOS differential pair in the RF input and the quad network, which allows them to be stacked and the current to be reused as shown in Figure 8.41 [4]. In such a case, th...

  • Page 302

    8.12 AlternativeMixerDesigns281no dc current flowing through the transistors; in fact, the RF inputs are typically ac coupled. Because there is no dc current, it is possible to operate this mixer at very low power and with low 1/f noise. The main disadvantage is that this mixer does not have gain...

  • Page 303

    282Mixershold circuit, samples the carrier at less than Nyquist, thus it is undersampling the carrier. However, the bandwidth of the signal should be less than half the sampling frequency; hence the signal is properly sampled. Because the sampling circuit is operating at lower frequency compared ...

  • Page 304

    8.12 AlternativeMixerDesigns283resistors. A design that stacks the entire circuit is unlikely, therefore, to fit into the 3.3-V supply requirement; thus it will have to be folded. Also, since we are using resistive degeneration, we can probably match the input with a simple resistor. Thus, the mi...

  • Page 305

    284Mixers=-=-=W´IP31.58216.6 71.233 6 mAEEeEEvRrISince this formula is an approximation and we have already included the effect of another nonlinearity, we will choose RE = 70W for this design.Next, we can find the load resistor noting that we want 15 dB of voltage gain or 5.6 volts-per-volt (V/...

  • Page 306

    8.12 AlternativeMixerDesigns285==×=(source)(source)nV1.29VnVHz 5.63.622VHznnovvvAThe other noise source of importance is RE. It produces a current in(RE) of==()4pA15.3HzEn REkTiRSince RE is significantly larger than re this current will mostly all go to the out-put, producing an output voltage v...

  • Page 307

    286MixersIIP3, the LO was set to be 400 mVpp at 1.95 GHz, and two RF signals were injected at 2.0 and 2.001 GHz. The fast Fourier transform (FFT) of the output voltage is plotted in Figure 8.46. From this figure, using a method identical to that used in the broadband LNA example in Section 7.9, i...

  • Page 308

    8.12 AlternativeMixerDesigns287Solution: For the LO path there is little additional design work to be done. For this ex-ample, we will ignore the square wave buffers that would normally be used to guarantee the mixer is driven properly. We add a simple phase shifting filter to the circuit like th...

  • Page 309

    288Mixersto reduced gain, but not too much, as now the noise due to the input has been im-age rejected as well.The components in the filters were then adjusted to show the effect of cir-cuit tolerance on the image rejection. Table 8.5 shows how the LO phase shifter affects image rejection. Note t...

  • Page 310

    8.12 AlternativeMixerDesigns289Note that the NF has dropped due to the increased gain. The linearity has been degraded slightly due to the addition of the additional nonlinearity of the output resistance of the PMOS transistors.One more improvement can be made to this circuit. The mixer can be pu...

  • Page 311

    290MixersSelected BibliographyLarson, L. E., (ed.), RF and Microwave Circuit Design for Wireless Communications, 2nd ed., Norwood, MA: Artech House, 1997.Maas, S. A., Microwave Mixers, 2nd ed., Norwood, MA: Artech House, 1993.Rudell, J. C., et al., “A 1.9-GHz Wide-Band IF Double Conversion CMOS...

  • Page 312

    291C h a p t e r 9Voltage Controlled Oscillators9.1  IntroductionAn oscillator is a circuit that generates a periodic waveform whether it be sinu-soidal, square, triangular as shown in Figure 9.1, or, more likely, some distorted combination of all three. Oscillators are used in a number of appl...

  • Page 313

    292 Voltage Controlled Oscillatorsthe analysis of a damped LC resonator such as the parallel resonator shown in Figure 9.2.Since there are two reactive components, this is a second-order system, which can exhibit oscillatory behavior if the losses are low or if energy is added to the circuit. It ...

  • Page 314

    9.3 Adding Negative Resistance Through Feedback to the Resonator 293add energy to the system as shown conceptually in Figure 9.4. If this parallel nega-tive resistance [Figure 9.4(a)] is smaller than the positive parallel resistance in the circuit, then any noise will start an oscillation whose ...

  • Page 315

    294 Voltage Controlled Oscillatorsrequired gain to result in oscillation. Later in the chapter we will see that we can use both an open loop and closed loop transfer function to analyze an oscillator.More formally, the system poles are defined by the denominator of (9.4). To find the poles of the...

  • Page 316

    some finite value, as shown in Figure 9.7. This reduces the effect of the negative resistance in the circuit until the losses are just canceled, which is equivalent to re-ducing the loop gain to 1.9.5  Configuration of the Amplifier (Colpitts or –Gm)The amplifier shown in Figure 9...

  • Page 317

    296 Voltage Controlled Oscillators9.6  Analysis of an Oscillator as a Feedback SystemIt can be instructive to apply the model of Figure 9.5 to the oscillator circuits dis-cussed above. Expressions for H1 and H2 can be found and used in either an open-loop analysis or a closed-loop...

  • Page 318

    9.6 Analysis of an Oscillator as a Feedback System 297At the emitter we have: 12110ecev sCsCv sCræö++-=ç÷èø (9.10)This can be solved in several ways; however, we will write it as a matrix expres-sion as: [ ][ ] 0Y v= (9.11)as in the following equation: 1111211001mpceesCsCgRsLvvsCsCsCréù+...

  • Page 319

    298 Voltage Controlled Oscillatorsresonating with the series combination of C1 and C2 as well as by noting that the Q of an inductor in parallel with a resistor is given by pLRQLω= (9.16)Then: 2212121111()()/ooooe ppeLcLLr R CCRr CCQωωωωωωωω ω=+=+×=+++ (9.17)where wc is the corner freq...

  • Page 320

    9.6 Analysis of an Oscillator as a Feedback System 299The passband gain Ao is given by 112oCACC=+ (9.20)The corner frequency wc is given by 121()cer CCω =+ (9.21)and the phase shift of the feedback network is 1tan2cπωφω- æö= -ç÷èø (9.22)If the frequency of operation is well above the...

  • Page 321

    300 Voltage Controlled Oscillatorsfor the Colpitts common base oscillator, and 21,tank21eeCrrCæö=+ç÷èø (9.24)for the common collector oscillator. The resulting transformed circuit as seen by the resonator is shown in Figure 9.13.Therefore, in order to get the maximum effect of the impedance...

  • Page 322

    9.6 Analysis of an Oscillator as a Feedback System 301Here, it can be seen that a transformation of 25 is about as high as is possible at this frequency and with the specified component limits as shown in the first row. Note that L and C2 are still on the high side, indicating that designing an ...

  • Page 323

    302 Voltage Controlled Oscillators tankFB12121||||11(1)1()LpepeZZRZj Cj r Cj L Rj r CCωωωω==+++++ (9.27) 12tank1212(1())()(1())(1)pepepej LRj r CCZRj Lj r CCj LR j Cj r Cωωωωωωω++=++++×+ (9.28)Feedback GainThe feedback circuit is just a highpass filter as described in the previous sec...

  • Page 324

    9.6 Analysis of an Oscillator as a Feedback System 303Gathering terms: 2112m epg r C LRA H HBω-×== (9.31)where B = (-jw 3)reC1C2LRp + (–w 2)[re(C1 + C2)L + RpC1L] + jw[reRp(C1 + C2) + L] + RpTo determine oscillating conditions, (9.31) can be set equal to 1, and then the real and imaginar...

  • Page 325

    304 Voltage Controlled OscillatorsThe remaining real terms can be used to obtain an expression for the required gm: 12,tank111mpeCCgRrCæö+æö=+× ç÷ç÷ èøèø (9.37)where CT, as before, is the series combination of C1 and C2. This final expression can be manipulated to show it is equal to...

  • Page 326

    9.7 Negative Resistance Generated by the Amplifier 305This can be solved for vp¢ noting that gm » 1/re. 2iivj Cπω¢ = (9.40)Another equation can be written for vce. ce1imig vvj Cπω¢+= (9.41)Substituting (9.40) into (9.41) gives: 121m iceig ivij Cj Cωωæö æö=+ç÷ ç÷èø èø (9.42)...

  • Page 327

    306 Voltage Controlled Oscillatorsresonance is actually a parallel one, the series components need to be converted back to parallel ones. However, if the equivalent Q of the RC circuit is high, the parallel capacitor, Cp will be approximately equal to the series capacitor Cs, and the above analys...

  • Page 328

    9.7 Negative Resistance Generated by the Amplifier 307This results in a new resonator resonant frequency ofω ===´par117.76150 Grad / s10 nH 1.66 pFLCThis is a frequency of 1.2353 GHz, which is close to a 10% change in fre-quency. The oscillating frequency is determined by resonance of the loop,...

  • Page 329

    308 Voltage Controlled OscillatorsAn expression for the current that flows into the circuit can be written as follows: 112212iimmeevig vg vrrππ=--+ (9.45)Now, if it is assumed that both transistors are biased identically, then gm1 = gm2, re1 = re2, vp1 = vp2, and the equation can be solved for...

  • Page 330

    9.8 Comments on Oscillator Analysis 309neg222311total120mmrggCC CCωω¶-=+=¶This leads to1total2CC=which means that the maximum obtainable negative resistance is achieved when the two capacitors are equal in value and twice the total capacitance. In this case C1 = C2 = 1.1258 pF.Now the loss i...

  • Page 331

    310 Voltage Controlled Oscillatorswell-designed oscillator, the predicted results will give a reasonable estimate of the performance. Then to refine the design, it is necessary to simulate the circuit.Example 9.5: Oscillator Frequency Shifts and Open-Loop GainExplore the predicted frequency with ...

  • Page 332

    9.10 A Modified Common-Collector Colpitts Oscillator with Buffering 311gain of 3 is optimal for output power [2]. Fortunately, this is close to the optimum value for phase noise performance.9.9  Basic Differential Oscillator TopologiesThe three main oscillators discussed so far can be ma...

  • Page 333

    312 Voltage Controlled OscillatorsThese stages add complexity and require current. One design that gets around this problem is shown in Figure 9.22. Here, the common-collector oscillator is modified slightly by the addition of resistors placed in the collector [3, 4]. The output is then taken fro...

  • Page 334

    are at the same dc voltage. If this circuit is made with bipolar transistors, the maxi-mum voltage swing that can be obtained is about 0.8V. That is to say, the voltage on one side of the resonator drops about 0.4V, while the voltage on the other side of the oscillator rises by about 0.4V. This m...

  • Page 335

    314 Voltage Controlled OscillatorsAnother variation on this topology is to use a transformer instead of capacitors to decouple the collectors from the bases, as shown in Figure 9.24 [5]. Since the bias can be applied through the center tap of the transformer, there is no longer a need for the RF ...

  • Page 336

    9.12 The Effect of Parasitics on the Frequency of Oscillation 315noise filter is that before startup, the transistor Q3 can be biased in saturation, be-cause during startup the second harmonic will cause a dc bias shift at the collector of Q3, pulling it out of saturation and into the active reg...

  • Page 337

    316 Voltage Controlled Oscillatorsoutput swing, it is usually desirable to make the inductance as large as possible (this will also make the oscillator less sensitive to parasitic resistance). However, it should be noted that large monolithic inductors suffer from limited Q. In addition, as the c...

  • Page 338

    9.14 Bias Shifting During Startup 317The saturation/triode and cutoff linearity constraint will also put a practical limit on the maximum power that can be obtained from an oscillator. After reach-ing this limit, increasing the bias current will have very little effect on the output swing. Altho...

  • Page 339

    318 Voltage Controlled Oscillatorsnot symmetric. They have no negative-going swing so they can change the average voltage or current at a node. Thus, they tend to raise the voltage at any node with signal swing on it, and after startup, bias conditions may shift significantly from what would be p...

  • Page 340

    9.15 Colpitts Oscillator Amplitude 319 fund02( )cos( )Tcii tt dtTω=ò (9.52)This can be solved by assuming a waveform for ic(t). However, solving this equation can be avoided by noting that the current pulses are very narrow, and therefore, the cosine can be approximated as unity and integratio...

  • Page 341

    320 Voltage Controlled OscillatorsThis is in parallel with all other losses in the resonator Rp: ==+total221//1ppmmpRRRG nG n R (9.57)We can plug this back into the original expression: tankbias221pmpRVIG n R=+ (9.58)Now we also know that bias12mIGV= (9.59)and that 21tanktank12CVVnVCC==+ (9.60)Th...

  • Page 342

    9.17 Phase Noise 321positive swing is expected to go to 2VDD for a peak swing of VDD per side, or peak swing of 2VDD for a differential output. Similarly, for a PMOS-only oscillator, the outputs are nominally at ground potential, and pulled up by the PMOS switches towards VDD. This peak positive...

  • Page 343

    322 Voltage Controlled Oscillators9.17.1  Linear or Additive Phase Noise and Leeson’s FormulaIn order to derive a formula for phase noise in an oscillator, we will start with the feedback model of an oscillator as shown in Figure 9.31 [7].From control theory, it is known that ou...

  • Page 344

    9.17 Phase Noise 323 22dHdddφωω= (9.73)Now substituting (9.73) back into (9.70), 221out2in2( )( )()HNsN sddφωω=D (9.74)This can be rewritten again with the help of the definition of Q given in Chapter 5: 2221out22in( )( )4()oHNsN sQωω=D (9.75)In the special case for which the feedback p...

  • Page 345

    324 Voltage Controlled Oscillatorsof a cycle for which the transistors are completely switched, int is the noise current injected into the oscillator from the biasing network during this time. During transi-tions, the transistors act like an amplifier, and thus collector shot noise icn from the r...

  • Page 346

    9.17 Phase Noise 325noise NIN is injected into the resonator. Thus |H1|=|H|=1 at the top of the resona-tor. However, at other points in the loop, the signal level is not the same as at the resonator. For instance, in the case of the common-base Colpitts oscillator, when looking at the midpoint b...

  • Page 347

    326 Voltage Controlled OscillatorsThus, the parallel resistance due to the capacitor will be===W××ωπ/total504,712.9(2 5 GHz) 337.7 fFp CQrCThus, the equivalent parallel resistance of the resonator is 1,087.5W.With a supply of 1.8V and a power consumption of 1 mW, the maximum cur-rent that the...

  • Page 348

    9.17 Phase Noise 327Solution: Since the Q of the inductor is constant regardless of inductor size and it is the only loss in the resonator, then the Q of the resonator will be constant.The parallel resistance of the resonator will be given byindpoRQLω=For low values of inductor, Rp will be smal...

  • Page 349

    328 Voltage Controlled OscillatorsAgain everything else is constant except for the power term, so 1PNSLPµµ Thus, once the amplitude has reached its maximum making the inductor any bigger will tend to increase the phase noise. These two curves will intersect at this point. Therefore, we can draw...

  • Page 350

    9.17 Phase Noise 329Example 9.8: Control Line Noise ProblemsA VCO designer has designed a VCO to operate between 5.7 and 6.2 GHz, and the tuning voltage is set to give this range as it is tuned between 1.5V and 2.5V. The design has been simulated to have a phase noise of -105 dBc/Hz at a 100-kHz...

  • Page 351

    330 Voltage Controlled OscillatorsThe magnitude of this noise can be estimated by a power series analysis as in the first edition of this book to show that the two tones are of equal magnitude. Alternatively, one can treat the transistor under large-signal operation as a sampling circuit, and by ...

  • Page 352

    9.18 Making the Oscillator Tunable 331function of time. For example, noise injected at the zero crossing would produces a large change in phase, and hence a large amount of phase noise while at the peaks, injected noise only produces a small change in phase. This time-varying transfer function,...

  • Page 353

    332 Voltage Controlled Oscillatorssubstrate. Unlike the desired pn junction, which has a high Q, this parasitic junction has a low Q due to the lower doping of the substrate. This makes it desirable to remove it from the circuit. This can be done by placing the varactors in the circuit such that ...

  • Page 354

    9.18 Making the Oscillator Tunable 333Another technique is to use the gate as one terminal and the substrate connec-tion as the other. In such a case, source and drain are not required. Such a varactor is often called the accumulation MOS, or AMOS varactor, since the capacitance is highest when ...

  • Page 355

    334 Voltage Controlled Oscillatorscapacitance between the gate oxide and the depletion capacitance. Note that while the holes are conductive, they do not connect to the n-type anode and hence do not short out the depletion capacitance.According to [14], using minimum channel length results in the...

  • Page 356

    9.18 Making the Oscillator Tunable 335where rcur is the output impedance of the current source and the transistors are as-sumed to be identical.This impedance given by (9.89) could easily be in the tens of ohms. Compare this to the circuit shown in Figure 9.23. In the case of Figure 9.23, noise ...

  • Page 357

    336 Voltage Controlled Oscillatorstypically requires both positive and negative voltages. To obtain the maximum tun-ing range with such a varactor, there is no choice but to place in it in the circuit without the terminals connected to VCC. Example 9.10: Colpitts VCO DesignConsider the Colpitts V...

  • Page 358

    9.18 Making the Oscillator Tunable 337Now the capacitance must be broken between C1 and Cvar . Since the re of the transistors will load the resonator, we would like to transform this resistance to a higher value. This can be done to greatest advantage if C1 is made larger than Cvar . However, w...

  • Page 359

    338 Voltage Controlled OscillatorsAs another check, the emitter swing will only be 0.55.0.8V = 0.44V. So if they are biased at 0.8V, then they should swing between 0.8 and about 0.35 just at the bot-tom of the swing, which should be fine. The collector is biased at about 100 mV below supply. The ...

  • Page 360

    9.18 Making the Oscillator Tunable 339Determining the Phase Noise of the VCOWe can also estimate the phase noise of this oscillator.The re of the transistor at this bias is===W25 mV14.61.71 mATeCvrISince this value will seriously affect our estimate, we also take into ac-count 5W for parasitic e...

  • Page 361

    340 Voltage Controlled OscillatorsVCO Simulation ResultsThe oscillator was simulated and the following results will now be shown.Transistor voltage waveforms can be seen in Figure 9.45. Note that the transis-tor safely avoids saturating. Also note that emitter voltage stays above 0.5V, leaving th...

  • Page 362

    9.18 Making the Oscillator Tunable 341The differential resonator voltage is shown in Figure 9.48. It is much more sinu-soidal as it is filtered by the LC resonator. The peak voltage is around 1.8V, which is only slightly higher than the simple estimate (1.6V) we did earlier.The tuning voltage ve...

  • Page 363

    342 Voltage Controlled Oscillatorsat the output and a phase noise of better than -110 dBc/Hz at a 1-MHz offset. As-sume that RL = 500W. Solution: The oscillator schematic is shown in Figure 9.51.Bias Currents and Transistor Sizes to Achieve Required Voltage SwingThe first step is typically to set...

  • Page 364

    9.18 Making the Oscillator Tunable 343This provides the required current, inductance product. To save power, low current and high inductance is picked. However, the maximum inductor size is limited by the need to keep the self-resonant frequency well above the operating frequency, and with low c...

  • Page 365

    344 Voltage Controlled OscillatorsFrom varactor simulations, it was determined that the AMOS varactors avail-able in this process could achieve a Q of about 30 or over if measured from the gate side, and a Cmax/Cmin ratio of about 2.5 if biased at 0.6V; however, this ratio drops to only about 1.4...

  • Page 366

    9.18 Making the Oscillator Tunable 345This is adequate, but with a number of assumptions made. In addition, there is the phase noise due to the tuning line. For this, the oscillator gain must be known. From the varactor characterization, at the lowest frequency when the capacitance is largest, t...

  • Page 367

    346 Voltage Controlled OscillatorsComputer Simulation ResultsSimulations were then done to verify performance. First it was verified that the oscillator could operate across the desired frequency range. Figure 9.52(a) shows frequency from about 6.98 GHz to about 7.43 GHz. It also verifies that th...

  • Page 368

    9.19 Low-Frequency Phase-Noise Upconversion Reduction Techniques 347but is swinging from about 0.5 to 1.5 mA with an average value of about 1.1 mA. The transition time for each transistor can be estimated as about 10% of the total period, thus the noise figure prediction could be modified accord...

  • Page 369

    348 Voltage Controlled Oscillatorsupconversion. Note that to get full switching, both positive and negative control voltages must be supplied. This is conveniently obtained when the oscillator has both NMOS and PMOS cross coupling, since the output nodes are nominally bi-ased between the power su...

  • Page 370

    9.19 Low-Frequency Phase-Noise Upconversion Reduction Techniques 349that with a 3:1 capacitance ratio, there is some difficulty in getting uniform curves.9.19.2  gm Matching and Waveform SymmetryIt is often stated that phase noise upconversion can be reduced by matching the transcondu...

  • Page 371

    350 Voltage Controlled Oscillators oxDSoxDS22pnnpnppnnpnpWWCICILLWWLLµµµµ== (9.91)These two conditions mean that for best phase noise, the ratio of the lengths of the transistors should be: nnppLLµµ= (9.92)where Lp is usually set to the minimum allowed by the technology and the ratio of the...

  • Page 372

    9.19 Low-Frequency Phase-Noise Upconversion Reduction Techniques 351varactors see a negative voltage. Hence, both varactors are increased in capacitance for an increase in differential input voltage. However, for a common-mode voltage, both varactors see a voltage in the same direction; hence, t...

  • Page 373

    352 Voltage Controlled Oscillatorsmaximum peak-to-peak swing for this design will be 1.2V. The current should be set to give this amplitude for lowest phase noise, but more current will be wasted and lead to excess noise. Therefore, for the complementary design the current should be set so that t...

  • Page 374

    9.20 VCO Automatic-Amplitude Control Circuits 3539.20  VCO Automatic-Amplitude Control CircuitsThe purpose of adding automatic-amplitude control (AAC) to a VCO design is to create a VCO with good phase noise and very robust performance over process, temperature, and frequency variations [...

  • Page 375

    354 Voltage Controlled OscillatorsTransistors Q3 and Q4 limit the amplitude of the oscillation directly, but are also the basis for the feedback loop that is the second mechanism used to make sure that the VCO is operating at an optimal level. Once these transistors start to turn on, they start t...

  • Page 376

    9.20 VCO Automatic-Amplitude Control Circuits 355diode connected transistor Q5 and C. This voltage is converted into the current Itank by Q6. Thus, the transfer function for this part of the loop is given by 6tank15bias( )( )( )mmgIsCA sgIssC=@+ (9.95)This equation has a dominant pole at 51mgPC@ ...

  • Page 377

    356 Voltage Controlled OscillatorsIt is interesting to note that a resonator with higher Q will respond more slowly and therefore have a lower frequency pole than a low-Q oscillator. This makes intuitive sense, since it is up to the losses in the resonator to cause a change in amplitude. The las...

  • Page 378

    9.20 VCO Automatic-Amplitude Control Circuits 357Example 9.13: The Design of a VCO AAC LoopDesign an AAC loop for the VCO schematic shown in Figure 9.60. Use L = 5 nH (Q = 10), VCC = 5V. The AAC loop should be set up so that the dc gain around the loop is 40 dB to ensure that the final dc current...

  • Page 379

    358 Voltage Controlled Oscillators==××=33Loop Gain 40 dB 20log(10 399)mA25.1VAAThus, from (9.101) we can size the limiting transistors to give the requred gain:ππππππ---éùêúêú=-Þ=-êúêúêúëûéùêúêú=-=×êúêúêúëûtanktanktanktank122223333tanktank22tanktank11.7V1.7V2...

  • Page 380

    9.20 VCO Automatic-Amplitude Control Circuits 359Example 9.14: Improvements to an AAC Loop Make some suggestions about how to improve stability and simulate a preliminary design. Solution:Let us assume that the inductance is still fixed; thus, the pole in the oscillator can-not be adjusted. One o...

  • Page 381

    360 Voltage Controlled Oscillatorsbe moved to a much higher frequency (say, 3 GHz), but then the second harmonic would not be attenuated by the loop, which could lead to other problems. Note that the gain and amount of pole separation are still not enough to make the design practical. If we were ...

  • Page 382

    9.20 VCO Automatic-Amplitude Control Circuits 361Figure 9.65 shows the current in transistor Q6. Note that we have started the reference current at almost 8 mA. Once the loop begins to operate, it brings this current back to a value necessary to give the designed amplitude. This is about 4.5 mA....

  • Page 383

    362 Voltage Controlled Oscillators9.21  Supply Noise Filters in Oscillators, Example CircuitAs discussed in previous sections oscillator noise is a very important topic. Often off-chip supply regulators used with IC chips may be insufficient to clean the supply noise to a level whe...

  • Page 384

    9.22 Ring Oscillators 363is set by a current source Ibias. It is necessary to move the resistor out of the supply path and use the transistor and op-amp because the resistor’s value will have to be quite high to get a filter with a cutoff frequency below 1 MHz, which is what is typically requi...

  • Page 385

    364 Voltage Controlled OscillatorsSo why, in fact, does it not oscillate? The answer is quite simple; it does not have the required phase shift. The phase shift around that loop is only 180°, which is 180° short of the required 360°. So the next question is: Can two inverters oscillate? As for...

  • Page 386

    9.22 Ring Oscillators 365negative transconductors driving RC loads as shown in Figure 9.74. Each stage is assumed to have a current gain of -Gm from input to output. Therefore, the voltage gain from input to output of one stage is: -==+outin( )1mvG RG svsCR (9.102)As a result, for three stages t...

  • Page 387

    366 Voltage Controlled OscillatorsFor oscillations in steady state, the loop gain must equal 1. Therefore: osc3osc113mG Rjω ωωω=æöç÷-=ç÷ç÷+èø (9.107)With some manipulation: 3()8mG R-= - (9.108)Therefore: 2mG R= (9.109)Similarly, for a four-stage ring oscillator, the required phase s...

  • Page 388

    9.22 Ring Oscillators 367With N stages and noting that (9.113) represents half a cycle, the period can be predicted as follows: ==DD22DDC VNCVTNII (9.114)or equivalently the frequency is given by: ==osc1DDIfTNCV (9.115)As a quick example, if a capacitance as low as 20 fF can be used, to achieve ...

  • Page 389

    368 Voltage Controlled OscillatorsSince oscillating frequency depends on how quickly the interstage capacitance is being charged, the bias current can be used to control the oscillating frequency. To form a differential inverter, it may be tempting simply to combine two of the single-ended invert...

  • Page 390

    9.22 Ring Oscillators 3699.80(b). In such a circuit, the current source ISS must be designed to be larger so it can pull down the output voltage when appropriate. For example, ISS can be made to be twice the current I3 or I4 in the PMOS transistors. In Figure 9.80(b), if Ictrl1 is equal to Ictrl...

  • Page 391

    370 Voltage Controlled Oscillators Recently, there have been many designs in which the PMOS current sources are controlled not from the previous stage, but by an earlier stage (being careful to get the polarity right) in order to compensate for the slower speed of PMOS compared to NMOS. While suc...

  • Page 392

    9.22 Ring Oscillators 371parameters work quite well for ring oscillators with few stages, as the output tends to be quasi-sinusoidal. For rings with a large number of delay cells, if there is more complete switching, such analyses may be less accurate. More detailed discussion of phase noise and...

  • Page 393

    372 Voltage Controlled OscillatorsNow we take the magnitude of this expression at wosc : osc2622oscosc27()272564mdHG Rdω ωωωω=== (9.119)By combining (9.74) and (9.119), we get: 22outosc22in21427()()NNdHdωωωω==DD (9.120)Now this is input noise in terms of voltage. Since we have a current...

  • Page 394

    9.22 Ring Oscillators 373Therefore, the phase noise will be equal to: 2osc2osc8()9kT RPNvωωωæöD =ç÷èøD (9.128)where vosc2 is the amplitude of oscillation squared. This is an approximate expres-sion for a three-stage ring oscillator. For a four-stage ring oscillator: osc22osc8dHdω ωω...

  • Page 395

    374 Voltage Controlled Oscillatorsfour-stage ring oscillator can be obtained by combining (9.131) with the knowledge that wosc = 1/RC resulting in: 2osc2oscosc2()kTPNvCωωωωæöD =ç÷èøD (9.133)Thus, comparing (9.132) with (9.133) we see that with resistance R removed from the equations, ph...

  • Page 396

    9.22 Ring Oscillators 375Transistor sizing was done by considering current for maximum fT. In this pro-cess, it is not practical to operate at maximum fT, since this requires a gate to source voltage close to the power supply voltage. Instead, if the transistor size is increased by about five ti...

  • Page 397

    376 Voltage Controlled Oscillators9.23  Quadrature Oscillators and Injection LockingIf, rather than noise, a signal is injected into an oscillator and if that signal is large enough, then it will pull the oscillator to that frequency. This phenomenon is known as injection locking. To st...

  • Page 398

    9.23 Quadrature Oscillators and Injection Locking 377Under large signal conditions, the negative and positive resistances in parallel nearly cancel out, resulting in a nearly ideal resonant circuit such that the noise in-put is amplified to produce the large signal oscillator output voltage vout...

  • Page 399

    378 Voltage Controlled Oscillatorsand the -3-dB bandwidth is given by: 1BRC= (9.137)The output voltage at resonance is given by: =outnvi R (9.138)When another signal iinj is coupled into an oscillator, whether deliberately or by accident, the output will be the gain times the input signal. If th...

  • Page 400

    9.23 Quadrature Oscillators and Injection Locking 379 23123i k v k vk v=+++ � (9.141)For small signals, k1 can be seen as gm. However, for larger signals the third-order term will produce components at the fundamental frequency and if k3 is negative will result in a decrease in the effective v...

  • Page 401

    380 Voltage Controlled Oscillatorswhere (f - f0) is the frequency offset from the oscillator free-running frequency. Thus, for larger offsets, the injected signal needs to be stronger. Note that an oscil-lator can also injection lock to a harmonic of a signal, and the above analysis can be used t...

  • Page 402

    9.23 Quadrature Oscillators and Injection Locking 381It is interesting to note that this has been interpreted to mean that the output voltage depends on the original parallel resistance and hence Q of the tank circuit. However, Rp and QU can both be eliminated from this expression by noting that...

  • Page 403

    382 Voltage Controlled OscillatorsNote that if the amplitudes of current were the same, (as will be the case in the quadrature oscillator to be discussed in a following section) then the phase shift finj would be twice that required by the bandpass filter fosc. 1injosc122tanCRLφφωω- éùæö=...

  • Page 404

    9.23 Quadrature Oscillators and Injection Locking 383has a gain and a phase as shown in Figure 9.87. We note that, as for any oscillator structure, the loop phase must be 0° or 360°. Thus, since the crossed wires at the output represent a phase shift of 180°, the two oscillators together must...

  • Page 405

    384 Voltage Controlled OscillatorsIn the special case where phase is 90°, the filter has a phase shift of 45° that occurs at: 229000422BBBωωω° =+±»± (9.158)where the approximation is valid if the center frequency is much larger than the bandwidth. In practice, these equations work well ...

  • Page 406

    9.23 Quadrature Oscillators and Injection Locking 385 21 0mLCLgωω±- = (9.160)The plus or minus of the middle term is used because one can find two solu-tions. One solution is below the resonant frequency, and one is above the resonant frequency. The solution for w is: 22021224mgmgBLCCCωω=+...

  • Page 407

    386 Voltage Controlled Oscillatorsapproximately at a frequency shift of d/4 (or 0.25%). From the starting frequency of 1.0519 GHz, a 0.25% shift would move it to 1.0493 GHz, while the equation and Figure 9.94 predict a new frequency of 1.0492 GHz. Both are close to the simulated frequency of 1.04...

  • Page 408

    9.23 Quadrature Oscillators and Injection Locking 387again in agreement with the simulations. Phase shift can be shown to be related to bandwidth by: 22odQdBφωω== (9.162)Hence, the phase shift is estimated at: matched/ 4/ 2/ 2BBωωδφD×D == (9.163)where d is the capacitor mismatch (0.01), ...

  • Page 409

    388 Voltage Controlled Oscillatorstransistor were approximately the same size. For the series circuit, the coupling transistors should be about five times bigger than the main transistors. For optimal coupling, the parallel circuit appeared to have better quadrature phase matching; however, if it...

  • Page 410

    9.24 Other Oscillators 3899.24  Other Oscillators Although we have stressed LC-based VCOs in this chapter as the most common RF oscillators due to their excellent phase noise, there are many other ways to build a circuit that generates harmonic waveforms. For example, we have already discu...

  • Page 411

    390 Voltage Controlled Oscillators For oscillator applications, the figure of merit, M, is a useful indicator that is defined as: 0 112 sMf C Rπ= (9.165)For M less than 2, the crystal reactance is never inductive at any frequency, and an additional inductor would be required to form an osci...

  • Page 412

    9.24 Other Oscillators 391For resonators with a large figure of merit (M > 5), fr can be approximated by: 112rsffQMéù=+êúëû (9.168)Table 9.3 presents some typical parameters as found on product data sheets, for example, in [34].The impedance of the crystal can be plotted as in Figure 9....

  • Page 413

    392 Voltage Controlled OscillatorsAn empirical formula to describe crystal oscillator phase noise is given by: 2016 1PN( ) 10112cLffff Qf- ±éù éùæöêúD =× ++êúç÷D ×Dèøêú ëûëû (9.170)where f0 is the oscillator output frequency, Df is the offset frequency, and fc is the corner...

  • Page 414

    9.24 Other Oscillators 393will have significantly lower phase noise and lower power dissipation than LC or ring oscillators. However, typically the purpose of a crystal oscillator is to achieve ultra-high stability, of the order of parts per million. To accomplish this, a complete commercial cry...

  • Page 415

    394 Voltage Controlled Oscillators[11] Mazzanti, A., and P. Andreani, “A 1.4mW 4.90-to-5.65GHz Class-C CMOS VCO with an Average FoM of 194.5dBc/Hz,” Proc. Int. Symp. Solid-State Circuits, February 2008, pp. 474–475.[12] Andreani, P., and S. Mattison, “On the Use of MOS Varactors in RF VC...

  • Page 416

    9.24 Other Oscillators 395[33] Vig, J. R., Quartz Crystal Resonators and Oscillators, U.S. Army Electronics Technology and Devices Report, SLCET-TR-88-1, 1988.[34] “Resonator Products,” Piezo Technology Inc., Orlando, Florida, http://www.piezotech.com/Resonators/resonatorsindex.htm.[35] Wata...

  • Page 417

  • Page 418

    397c h a p t e r 1 0Frequency Synthesis10.1  IntroductionThere are many ways to realize synthesizers, but possibly the most common is based on a phase-locked loop (PLL). PLL-based synthesizers can be further subdi-vided by which type of a division is used in the feedback path. The division rati...

  • Page 419

    398 Frequency Synthesisinteger-N frequency synthesizer. Circuits inside the feedback loop can be described by their transfer functions. These transfer functions can be designed to engineer the system dynamics to meet design specifications for the synthesizer. Typically, F(s) is realized with a lo...

  • Page 420

    10.3 PLL Components 399frequency must be made smaller. This is often undesirable so instead a fractional-N design is often used. This will be discussed later.10.3  PLL ComponentsWe will now briefly look at the basic components needed to make a PLL-based synthesizer and their basic governing ...

  • Page 421

    400 Frequency SynthesisHowever, we would like to have an expression relating input voltage to output phase since the output of the VCO ultimately goes to the phase detector. To relate frequency w to phase q, we note that: ddtθω = (10.5)Therefore, the output phase of the VCO can be given as: VCO...

  • Page 422

    10.3 PLL Components 401ence phase (vR) is ahead of the output phase (vo), then the circuit produces a signal UP that tells the VCO to speed up and therefore advance its phase to catch up with the reference phase. Conversely, if the reference phase is lagging the output phase, it produces a signa...

  • Page 423

    402 Frequency Synthesismiddle state, the tri-state where both outputs are zero. Then, depending on which edge arrives first, the PFD moves either to the up state or to the down state. If the reference edge arrives first, the output needs to catch up and so the up switch turns on to charge up the ...

  • Page 424

    10.3 PLL Components 403note that any positive phase, for example, 60º, for which the output current would be I ´ 60/360, could be interpreted as the equivalent negative phase, for example, +60º is equivalent to -300º, for which the current is equal to -I ´ 300/360. Thus, for every phase dif...

  • Page 425

    404 Frequency SynthesisIn addition, lowpass filtering is needed since it is not desirable to feed pulses into the VCO. This is usually done by dumping the charge produced by the charge pump onto the terminals of a capacitor. As we will show later, a simple capacitor all by itself does not yield a...

  • Page 426

    10.4 Continuous-Time Analysis for PLL Synthesizers 405This admittance can be used to determine vc, the control voltage of the VCO using (10.11): phase1phase121112()(1)()(1)(1)()(1)RoRodcsKsC RKsC RivYsC sC RsCs CCsC Rθθθθ-+-+===+ +++ (10.13)where 1 212sC CCCC=+ and phase2IKπ=.The frequency ...

  • Page 427

    406 Frequency SynthesisNow (10.14) is the most general PLL loop equation, and for specific loops it dif-fers only in the form that F(s) takes. For instance, in a first-order loop F(s) is simply equal to 1. In this case, the loop equation becomes: θθ=+oRKs K (10.16)Note that for this first-order...

  • Page 428

    10.4 Continuous-Time Analysis for PLL Synthesizers 407Thus, for this PLL, we get a second-order transfer function with a zero. Note the purpose of R can be seen directly from this equation. If R is set equal to zero, it can be seen by an inspection of (10.19) that the poles of this equation will...

  • Page 429

    408 Frequency Synthesisthe output frequency (as given by the control voltage) as a function of the input fre-quency, noting that frequency is the derivative of phase and starting from (10.25): éùæöêú++êúêúëûæö++22sssssssωζωπθζωωππωζωωζωω×éù++êúç÷êúèø×ê...

  • Page 430

    10.4 Continuous-Time Analysis for PLL Synthesizers 409Since this equation can be tedious without a calculator, two equations some-times used to approximate this are: 3dB3dB21.5 (approximation #1)(12)1.5 (approximation #2)nnωζωζωζωζ»>» +< (10.28)10.4.3  Complete Loop Transfe...

  • Page 431

    410 Frequency Synthesisthe gain is greater than 1. In fact, this is not the case and the system is stable. A full stability analysis, for example, by plotting the closed-loop poles, would show this. The closed-loop gain with C2 is given by: θθ+=++++VCO phase1212VCO phase1(1)()(1)(1)oRsKKsC Rs N...

  • Page 432

    10.5 Discrete Time Analysis for PLL Synthesizers 411where 44nnTTζ ωαζ ω-=+ (10.32) 2 2412nnTKTωζωæö=+ç÷èø (10.33)and T is the period of the reference.Starting from the closed loop transfer function, the pole locations as a function of the reference period T can be sketched and are...

  • Page 433

    412 Frequency SynthesisNow the poles of (10.31) are given by: 21Poles 1(2)4(1)22KKKα= -±--- (10.34)The pole that has the larger positive value is not of concern, because it will never leave the unit circle. However, it is of interest to find out when: 211(2)4(1)122KKKα-----= - (10.35)Skipping ...

  • Page 434

    10.6 Transient Behavior of PLLs 413example, the tri-state PDF has a linear range of ±2p. If an event at the input occurs that causes the phase error to exceed 2p, then the loop will experience a nonlinear event: cycle slipping. Remember that in the previous analysis it was assumed that the phas...

  • Page 435

    414 Frequency Synthesis ( )1ntenntt e ωωθωζω-D=×= (10.45) 22sin1( )11nntentte ζωωζωθζωζ-éù-D êú=<êú-ëû (10.46)These results are plotted in Figure 10.16 for various values of damping con-stant.It can be seen that a damping constant of 0.707 to 1 results in the fastest se...

  • Page 436

    10.6 Transient Behavior of PLLs 415given by: 22VCOVCOVCOC222222221222nnnnnnnnnnNNNsKKKsVsssssssωζζωωωωωωζωωζωωζωωæö×D+× D×ç÷èø D=×=+++++++ (10.49)Now the first term is simply a scaled version of the previous expression, and the second term is the integral of the first...

  • Page 437

    416 Frequency Synthesisuseful to compare with the control voltage (which is more readily available from simulation), they can also be misleading.Example 10.1: Limits of the Theory So FarAssume that a synthesizer is designed with a charge pump, PFD, and loop filter like the ones considered thus fa...

  • Page 438

    10.6 Transient Behavior of PLLs 417range, then the loop will never acquire lock. In addition, if the loop has a finite dc gain, then the range of lock acquisition may also be limited by the finite range of the phase detector. In general, a frequency step will result in a nonzero phase error. The...

  • Page 439

    418 Frequency SynthesisThus, one can see directly that as the loop bandwidth is expanded, the settling time will decrease as expected. Even though this is the main result in which we are inter-ested, a few more details of the transient behavior of the control voltage are very interesting to exami...

  • Page 440

    10.6 Transient Behavior of PLLs 419Example 10.2: Simulation and Estimation of Loop Settling TimesA 3.7–4.3-GHz synthesizer with a step size of 1 MHz is required. A 40-MHz crystal oscillator, a charge pump with a 2p×100 mA output current, and a VCO (operating from a 3-V supply) are available. ...

  • Page 441

    420 Frequency SynthesisSolution:First, if the VCO is operating with a 3-V supply and must have a 600-MHz tun-ing range, we can estimate that its KVCO will be 200 MHz/V. In addition, since we know the charge pump current, we know that that the Kphase will be 100 mA/rad. For a VCO with a nominal fr...

  • Page 442

    10.6 Transient Behavior of PLLs 421The second frequency step can be simulated as well. The results of this simula-tion are plotted in Figure 10.23 and compared to the linear voltage ramp suggested by simple theory previously. In this case, this plot shows that the nonlinear response is predicted...

  • Page 443

    422 Frequency Synthesis10.6.3  Various Noise Sources in PLL Synthesizers 10.6.3.1 VCO NoiseAll the circuits in the synthesizer contribute to the overall noise in different ways and the noise they produce has different characteristics. For instance, the phase noise from a VCO can be ...

  • Page 444

    10.6 Transient Behavior of PLLs 423dividers add to a signal [16, 17]: ωωϕωπ ωπ±- ±- ±- ±+D »++× D-14 127 1 222 1216 1Div_Added101010()1022dodo (10.60)where wdo is the divider output frequency and Dw is the offset frequency. Notice that the first term in (10.60) represents the flicke...

  • Page 445

    424 Frequency Synthesis10.6.3.6 Loop Filter NoiseLoop filters are simple RC circuits and can be analyzed for noise in the frequency domain in a linear manner. The most common loop filter that has been examined in this chapter will now be analyzed. It contains only one noise source, the thermal no...

  • Page 446

    10.6 Transient Behavior of PLLs 425 VCO phasenoise outVCO phasenoiseI( )( )( )( )sF s KKsF s KKsNϕϕ=+ (10.64)where for the charge pump PFD loop, the transfer function for the filter, divider, and crystal reference noise becomes: VCO1noise out1VCOVCO2noiseI1(1)( )2( )s22SIKRC ssCIKIKsRNNCϕπϕ...

  • Page 447

    426 Frequency SynthesisUsing our loop will give: =++××2noise outVCOVCO2noise II1( )( )22ssIKIKssRSNNCϕϕππ (10.67)This is a highpass filter. Thus, at low offsets inside the loop bandwidth, the VCO noise is suppressed by the feedback action of the loop, but outside the loop bandwidth, the VCO...

  • Page 448

    10.6 Transient Behavior of PLLs 427must be 1 MHz in order to get a step size of 1 MHz. Therefore, the division ratio will be 4,000. Knowing that we want a loop bandwidth of 150 kHz means that we need a natural frequency of 75 kHz (assuming a damping constant of 0.707), and this means that for th...

  • Page 449

    428 Frequency SynthesisTherefore, to plot phase noise in dBc/Hz, we take:136CP25112.22 10 (1 3 10)rad() 20log100Hz()6.66 102.22 10jPNnjjωωωω-æö×+ ×DD =×ç÷D+×D +×èøThe results of this calculation and similar ones for the other noise sources are shown in Figure 10.26. The total phase...

  • Page 450

    inside and outside of the loop bandwidth. In order to reduce the effect of charge pump noise, the loop bandwidth in this case should be reduced by at least two orders of magnitude. Note also the dramatic change in the in-band phase-noise performance between the two designs. While the fractional d...

  • Page 451

    430 Frequency SynthesisSolution:If an integer-N synthesizer were designed to service only one of these bands, then it would have a maximum reference frequency of 3 MHz in the first case and 4 MHz in the second case. However, if a synthesizer must be designed to cover both of these bands, then it...

  • Page 452

    will generate spurious components (or spurs) at integer multiples of the repetition rate of the time sequence. Such spurious components can be reduced by using SD modulators in which the instantaneous division ratio is randomized while maintain-ing the correct average value. 10.7.1  Fractional-...

  • Page 453

    432 Frequency SynthesisAs shown in the above example, for the K = 1 case, Cout is high for one cycle and low for seven cycles within every eight clock cycles, so the frequency of Cout is fclk/8. For the K = 3 case, Cout is high for three cycles and low for five cycles within every eight clock cyc...

  • Page 454

    tage that the range of frequencies over which the synthesizer can be tuned is ex-panded, compared to the previous architecture. The synthesizer output frequency is given by: éù=+êúëûVCOrfKfIRF (10.75)where I is the integer portion of the loop divisor and, depending on the complexity of the ...

  • Page 455

    434 Frequency Synthesis10.7.3  Fractional-N Spurious ComponentsThe above-discussed fractional-N architectures suffer from a common side effect of generating spurious components associated with periodically toggling the loop division ratio. Recall that any repeatable pattern in the time doma...

  • Page 456

    Figure 10.31  Measured output spectrum of a fractional-N frequency synthesizer with loop divisor N = 160 + 1/32 and the comparison frequency fr/R = 5.12 MHz.Figure 10.30  (a) Simulated fractional accumulator output with loop divisor N = 160 + 1/32 and (b) the comparison frequency fr/R = 5...

  • Page 457

    436 Frequency Synthesiscycles and divided by 161 for F-K cycles, which results in an average division ratio of 160 + K/F. As an example, for the second channel with K = 1 and F = 32, the simulated fractional accumulator output is given in Figure 10.30. As shown, the fractional accumulator outputs...

  • Page 458

    [7] Reinhardt, V. S., et al., “A Short Survey of Frequency Synthesizer Techniques,” Frequency Control Symposium, May 1986, pp. 355–365. [8] Rohde, U. L., Digital Frequency Synthesizers: Theory and Design, Upper Saddle River, NJ: Prentice-Hall, 1983. [9] Rohde, U. L., Microwave and Wireless...

  • Page 459

    438 Frequency Synthesis[31] Aytur, T., and B. Razavi, “A 2-GHz, 6-mW BiCMOS Frequency Synthesizer,” IEEE J. Solid-State Circuits, Vol. 30, December 1995, pp. 1457–1462.[32] Chen, W., et al., “A 2-V 2.3/4.6-GHz Dual-Band Frequency Synthesizer in 0.35-mm Digital CMOS Process,” IEEE J. Sol...

  • Page 460

    [51] Riley, T. A., M. Copeland, and T. Kwasniewski, “Delta–Sigma Modulation in Fractional-N Frequency Synthesis,” IEEE J. Solid-State Circuits, Vol. 28, May 1993, pp. 553–559.[52] Rogers, J. W. M., et al., “A DS Fractional-N Frequency Synthesizer with Multi-Band PMOS VCOs for 2.4 and 5 ...

  • Page 461

  • Page 462

    441c h a p t e r 11Power Amplifiers11.1  IntroductionPower amplifiers, also known as PAs, are used in the transmit side of RF circuits, typically to drive antennas. Power amplifiers typically trade off efficiency and lin-earity, and this trade-off is very important in a fully monolithic impleme...

  • Page 463

    442 Power Amplifiersprocesses, because of breakdown considerations, the fastest transistors are limited to an operating point of about 1V, limiting the maximum power to about 10 mW or 10 dBm when directly driving a 50W load. Higher power is often needed and, as we will see later, is in fact possi...

  • Page 464

    11.4 Matching Considerations 443Power-added efficiency (PAE) is the same as efficiency; however, it takes the gain of the amplifier into account as follows: outinoutoutdcdc/1PAEPPPPGPPGη--æö===1 -ç÷èø (11.5)where G is the power gain Pout /Pin. Thus, it can be seen that for high gain, pow...

  • Page 465

    444 Power Amplifiersfor high input power where the amplifier is nonlinear. Nonlinearities result in gain compression, the appearance of harmonics, and additional phase shift. The result can be a shift of the operating point and a shift in the optimal load impedance. For these reasons, for large-s...

  • Page 466

    11.5 Class A, B, and C Amplifiers 445operation and in Figure 11.8 for class B and C operation. For CMOS-based ampli-fiers, the input would be on the gate and the output on the drain. Class A amplifiers can be designed to have more gain than class B or class C amplifiers. However, as will be seen ...

  • Page 467

    446 Power AmplifiersFigure 11.7  Waveforms for a class A power amplifier.Figure 11.8  Power amplifier waveforms: (a) class B operation and (b) class C operation.

  • Page 468

    11.5 Class A, B, and C Amplifiers 447is flowing. If current is always flowing, the conduction angle is 360° and operation is class A. If the current flows for exactly half of the time, the conduction angle is 180° and operation is class B. For conduction angles between 180° and 360°, the oper...

  • Page 469

    448 Power Amplifiersbe some loss, since there is an overlap of nonzero voltage and current. Other classes of amplifiers, to be described in later sections, namely, classes D, E, and F, are de-signed such that the voltage across the transistor is also nonlinear, leading to higher efficiencies, in ...

  • Page 470

    11.5 Class A, B, and C Amplifiers 449Power supplied is given by CC CCCCCC dc(sincos )V IPV Iθ θθπ==- (11.9)The fundamental current i1 given by CC1CCCQ04(cos)cos( )[2sin2 ]22IiIt Itd tθωω ωθθππ=-=-ò (11.10)Output power is given by 2peakpeak1out222Lvii RP==× (11.11)The maximum possibl...

  • Page 471

    450 Power AmplifiersEquation (11.14) will be more convenient to plot if we eliminate ICC. Recall that ICC is a measure of the peak current, not with respect to zero, but with respect to the center of the sine wave where the center for class C is less than zero, as shown in Figure 11.12.The peak c...

  • Page 472

    11.5 Class A, B, and C Amplifiers 451 CC22cos sinsin cos(1)nInnnin nθθθθπéù-=êú-ëû (11.18)Figure 11.14 shows the current components normalized to the maximum cur-rent excursions in the transistor. The dc component is found from (11.8), the fun-damental component is found from (11.10), ...

  • Page 473

    452 Power Amplifiersangles, the collector current is rich in harmonics. However, the tuned circuit load will filter out most of these, leaving only the fundamental to make it through to the output.At very low conduction angles, the current “pulse” is very narrow approaching the form of an imp...

  • Page 474

    11.5 Class A, B, and C Amplifiers 453Note that this agrees with Figure 11.14, which showed the third and fifth har-monics passing through 0 when q = 90° (conduction angle is 180°). In the push-pull arrangement, the dc components and even harmonics cancel, but odd harmonics add, thus the output ...

  • Page 475

    454 Power Amplifiersor 22 0.2000.154 or 154 mA2.6oppPiv´===Thus, for class A, the nominal current should be about 154 mA with a peak excursion from about 0 to 308 mA. Thus, with the transistor as given, with peak fT at about 15 mA, let us choose to use 10 of these units. Then with operation clos...

  • Page 476

    11.5 Class A, B, and C Amplifiers 455the load (j7.6 if in series) accounts largely for the transistor output capacitance. The sweeps of Pout and power-added efficiency versus Pin shown in Figure 11.20 shows that 1-dB compression occurs at an input power of about 9 or 10 dBm and that power-added e...

  • Page 477

    456 Power Amplifiersthird curve shows Pin, the simulated actual input power, versus PAVS. If the circuit is matched, Pin should equal PAVS. Several differences can be seen between this simulation and simple theory. The simple equations were derived assuming that output voltage swings from 0V to 6...

  • Page 478

    11.5 Class A, B, and C Amplifiers 457is now 57.2% and the amplifier is now nonlinear. If instead the same amplifier is used as in Example 11.1, a bias current of 147 mA, the output power is increased to 24.1 dBm and efficiency is increased to 58.9%. Time-domain waveforms for this case can be seen...

  • Page 479

    458 Power AmplifiersSolution:The high-frequency transistors in the process have a suggested power supply volt-age of 1.2V and an oxide breakdown voltage (VDG or VGS) of about 1.6V. The drain voltage will have an average value equal to the power supply voltage; hence, it will not take much positiv...

  • Page 480

    11.5 Class A, B, and C Amplifiers 4591.8 + 1.5 or 3.3V. A class AB amplifier would be biased at somewhat lower cur-rent, for example, at 75 mA. It can be assumed that the IDS and VDS swing is the same as for the class A amplifier. Note that if VGS does not swing up to 2V as was assumed here, the ...

  • Page 481

    460 Power AmplifiersThis allows us to calculate the efficiency 2sin21.50.632 0.534(sincos )1.8opDDvVθθηθ θθ-==´=- For a CMOS amplifier, the gain may be as low as 3 dB, in which case we can predict the PAE as 110.265PAEGηæö=-=ç÷èø Then with the basic design completed, we do some sim...

  • Page 482

    11.5 Class A, B, and C Amplifiers 461load pull, the load inductance Ltank can be adjusted until the optimum load is close to the negative real axis on the Smith chart. Step 3: Fix the output impedance at the optimal value and match the in-put again. In spite of enhanced reverse isolation with th...

  • Page 483

    462 Power AmplifiersSimilarly, with the input at 15 dBm (and conjugately matched), the load pull pro-duced contours that were very similar except that the maximum output power was increased to 94.22 mW at nearly the same location on the Smith chart (about 21.4W) with the first contour at 91.66 mW...

  • Page 484

    11.6 Class D Amplifiers 463very close to that predicted by the single transistor curve. This is possible because the presence of the source inductance allows the source voltage of the driver transis-tor to go negative. The current swing for a 12.5-dBm input is from 0 to 200 mA, or for a 15-dBm i...

  • Page 485

    464 Power Amplifierscomponent and the harmonics, resulting in a sine wave at the output. Figure 11.29(b) shows the class D amplifier as usually implemented with two separate switches. While the switch making the connection to ground is straightforward to implement, the switch connecting to VCC is...

  • Page 486

    11.7 Class E Amplifiers 465The transistor Q1 behaves as perfect switch. When it is on, the collector volt-age is 0V, and when it is off, the collector current is zero.The transistor output capacitance co, and hence C, is independent of voltageWith the above approximations, the circuit can now be ...

  • Page 487

    466 Power Amplifiersreaches 0 as the switch turns on, no energy is lost and the efficiency is 100%. In practice, because the assumptions do not strictly hold and because components will not be ideal, the voltage will not be at zero and so energy will be lost. However, with careful design, efficie...

  • Page 488

    11.7 Class E Amplifiers 467and that 22CCCC220.5771/ 4oVVPRRπ»+ (11.24)The dc current is given by =CCdc1.734VIR (11.25)The peak transistor currents and voltages are given by ==C,peakCCs,peakdc3.562.86vViI (11.26)The resulting output power is 78% of the power produced by a class B PA, but the eff...

  • Page 489

    468 Power Amplifiers11.7.5  Transition TimeIdeally, no power is dissipated during the transition between off and on. The turn-on transition for nonoptimum conditions can be approximated with a linear ramp of current. This produces a parabolic collector voltage waveform. As described in [4], t...

  • Page 490

    11.7 Class E Amplifiers 469Lo therefore has a reactance of 37.2 + 78 = 115.2W and is thus 7.64 nH. Ideally, the RFC should have a reactance of at least 10R and thus should be at least 17 nH, which would likely need to be an off-chip inductor. This circuit was simulated using a bipolar process wit...

  • Page 491

    470 Power Amplifiersdc-to-RF efficiency of about 90%. However, with the unrealistic pulse input, a sig-nificant amount of power is fed into the input so PAE will be lower; in this exam-ple, with an input current of nearly 20 mA, PAE is estimated to be about 75%. 11.8  Class F AmplifiersIn t...

  • Page 492

    11.8 Class F Amplifiers 471collector voltage. At the correct amplitude and phase, this third-harmonic compo-nent produces a flattening of vC as shown in Figure 11.36. This results in higher efficiency and higher output power.If the amplitude of the fundamental component of the collector voltage i...

  • Page 493

    472 Power AmplifiersAs an aside comment, the Fourier series for the ideal square wave is 11sinsinsin5 ...35θθθ++ (11.34)However, choosing Vcm3 = 1/3Vcm would produce a nonflat waveform, as shown in Figure 11.37. The efficiency can be calculated as Po /Pdc. By taking a Fourier series of the iC...

  • Page 494

    11.8 Class F Amplifiers 473 omCC43VV= (11.36)and the efficiency is given by 884.9%3ηπ=» (11.37)11.8.2  Variation on Class F: Quarter-Wave Transmission LineA class F amplifier can also be built with a quarter-wave transmission line as shown in Figure 11.39, with waveforms shown in...

  • Page 495

    474 Power Amplifierswith the result that the collector voltage waveform is a square wave (assuming that the odd harmonics are at the right levels).The collector current consists of the fundamental component (due to the load resistor) and all even harmonics. We note there are no odd harmonics, sin...

  • Page 496

    11.9 Class G and H Amplifiers 475dccm0.23775.5 mAIiππ===Check powers, efficiencies Þ Pdc = Idc VCC = 0.0755 ´ 3 = 0.2264W dc0.2088.4%0.2264oPPη ==Þ Of course, in a real implementation, efficiency would be lower because of losses due to saturation voltage, on resistance, finite inductor Q, ...

  • Page 497

    476 Power AmplifiersThe power supplies use a highly efficient switching amplifier. Noise (from switching) is minimized by the power supply rejection of the linear amplifier.As with the class G amplifier, this technique has mainly been used for lower frequencies. However, this technique can be mod...

  • Page 498

    11.11 AC Load Line 477where the amplitude is not constant. Linearization techniques, to be discussed later, are not yet widely used for fully integrated power amplifiers.Class A, AB, and B amplifiers can achieve approximately the same fundamental RF output power. However, class B has a theoretica...

  • Page 499

    478 Power Amplifiersvoltage and current will be out of phase and the dynamic load line will no longer be a straight line, appearing instead as an ellipse. Figure 11.44 shows a simulated family of curves for increasing input amplitude from a 25-mV to a 200-mV peak. The amplifier is shown with an i...

  • Page 500

    11.12 Matching to Achieve Desired Power 479resistance R is approximately 4.5W. Similarly, for a Po of 500 mW, R needs to be approximately 9W, and for a Po of 200 mW, R needs to be about 22.5W.Generally, the smaller R is, compared to RL, the narrower will be the bandwidth of the circuit; that is, ...

  • Page 501

    480 Power Amplifiers11.13  Transistor SaturationEfficiency increases rapidly with increasing input signal level until saturation of the input device occurs. After the transistor saturation, efficiency is fairly con-stant, but drops somewhat due to gain compression and the resulting increase i...

  • Page 502

    11.14 Current Limits 481collector current can easily be over 1A. As a result, there is a requirement for huge transistors with very high current handling requirements. This requires the use of transistors with multiple fingers as shown in Figure 11.49 for a bipolar transistor, as well as multiple...

  • Page 503

    482 Power Amplifierslength is doubled, or for a CMOS transistor as the transistor width is doubled, the current is doubled. However, if the line width stays the same, the maximum cur-rent capability is the same. As an example, if the transistor current is 1 mA and line widths are appropriate to a...

  • Page 504

    11.17 Thermal Runaway—Ballasting 483the wavelength of a 1-GHz sine wave in free space is 30 cm. This results in a phase shift of about 1.2°/mm. Wavelength is inversely proportional to frequency and in-versely proportional to the square root of the dielectric constant eR. Thus, for SiO2 with eR...

  • Page 505

    484 Power Amplifiers =D» -D°constantmV2CBEIVT (11.38)Thus, if VBE is held constant, if temperature increases, current increases, and as a result, more power is dissipated and temperature will increase even more. This phenomenon is known as thermal runaway. Furthermore, for unbalanced transis-to...

  • Page 506

    11.18 Breakdown Voltage and Biasing 48511.18  Breakdown Voltage and BiasingAvalanche breakdown occurs when the electric field within the depletion layer provides sufficient energy for free carriers to knock off additional valence elec-trons from the lattice atoms. These secondary electron...

  • Page 507

    486 Power AmplifiersA complication during the design phase is that some transistor models are too simplistic and do not include the effects of breakdown. Clearly, while better simula-tion models are required, many designers depend on laboratory verifications, com-mon sense, and experience.11.19...

  • Page 508

    11.20 Effects and Implications of Nonlinearity 48711.20.3  Spectral RegrowthThere can be additional problems that are worse for systems with varying envelopes. As an example, envelope variations can occur for modulation schemes that have zero crossings, such as binary phase shift keying (BPSK...

  • Page 509

    488 Power Amplifiers11.20.5  FeedforwardThe feedforward technique is shown in Figure 11.55. The amplifier output is vM = AV vin + vD, which consists of AV vin, the amplified input signal, and distortion components vD, which we are trying to eliminate. This signal is attenuated to result in vN ...

  • Page 510

    11.21 CMOS Power Amplifier Examples 489severe. An example of using such a feedback technique is shown in Figure 11.56. There have been a number of variations on this technique, including techniques to remove envelope variations. The interested reader is referred to [7].11.20.7  PredistortionPre...

  • Page 511

    490 Power Amplifiersas switching circuits to deliver substantial power with relatively high efficiency. (Note that class C amplifiers are also high efficiency, however, only at low conduc-tion angles; thus, they provide high efficiency only at low power levels.) Measured results with a 2.5-V powe...

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    11.21 CMOS Power Amplifier Examples 491[11] Brama, R., et al., “A 30.5 dBm 48% PAE CMOS Class-E PA with Integrated Balun for RF Applications,” IEEE J. Solid-State Circuits, Vol. 43, No. 8, August 2008, pp. 1755–1762.[12] Gonzalez, G., Microwave Transistor Amplifiers, Analysis and Design, 2n...

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    493493About the AuthorsJohn W. M. Rogers received a Ph.D. in electrical engineering from Carleton University, Ottawa, Canada, in 2002. Concurrent with his Ph.D. research, he worked as part of a design team with SiGe Semiconductor that developed a cable modem IC for the DOCSIS standard. From 2002...

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  • Page 516

    495495IndexAAccumulatorsfractional, 432, 435in fractional-N synthesizers, 434–36simulation, 431–32spurious tones, 436AC load line, 477–78Admittancecorrelation, 188–89equivalent, 117open-loop, 380parameters, 126–28Smith chart, 104, 105AMOS varactorscross section, 333CV curve, 333differen...

  • Page 517

    496IndexBank switching, 347–49Barkhausen criteria, 294, 363Base pushout, 78Bias current, 200, 201–3BiasingCMOS transistors, 227–28mixers, 267power amplifiers, 485–86RFICs, 222Bias shifting, 317–18Bias voltage, 368BiCMOS, 87Binary frequency shift keying (BFSK), 36, 37, 487Binary phase sh...

  • Page 518

    Index497Charge pumps, 406, 416current, 418noise, 423second-order, 417Chip-on-board packaging, 169, 486Class A amplifiersanalysis, 448–52conduction angle and efficiency, 447current and voltage excursions, 447gain, 445output power, 445transconductance, 453–56waveforms, 446Class AB amplifiersbip...

  • Page 519

    498IndexCMOS transistors (continued)illustrated, 88layout for, 98NMOS, 88, 89–90noise, 92–98noise figure and noise factor determination, 97noise model, 94, 190–91nonlinearity in, 211output impedance, 211PMOS, 88, 90small-signal model, 90–92CMOS VCO, 341–47bias currents, 342–43computer...

  • Page 520

    Index499Conductive materials, 132Continuous-time analysis, PLL synthesizers, 405–10complete loop transfer function, 409–10frequency response and bandwidth, 408–9simplified loop equations, 405–8Control line noise, 329Control theory, 322Control voltages, 414, 415, 421Coplanar waveguides, 16...

  • Page 521

    500IndexDigital-to-analog converters (DAC), 45SNR of, 69specifications, 66–69Diodes, nonlinearity in, 19Direct conversion transceivers, 45–47Direct downconversion radios, 46Directional antennas, 70Discrete time analysis, PLL synthesizers, 410–12Distortioncomponents summary, 21predistortion,...

  • Page 522

    Index501Frequency dividersmultimodulus, 432–33noise, 422–23as PLL component, 399–400Frequency modulation, 36–38Frequency shift keying (FSK), 36–38, 486binary (BFSK), 36, 37bit error probability, 38symbol error probability, 37, 38Frequency shifts, 301, 307, 310–11Frequency synthesis, 3...

  • Page 523

    502IndexImpedance matching networks, 103highpass, 109, 110illustration of, 109lowpass, 109, 110with reactive components, 106regions and, 107–8Impedance transformation networks, 118–20Impulse sensitivity noise analysis, 330–31Inductancebond wire, 479calculation of, 136–37determining, 147...

  • Page 524

    Index503LLaplace transform, 413–14LC resonators, 291–92, 295Leeson’s formula, 330, 391Linearityin amplifiers, 205–14bipolar differential pair, 217blockers and, 58–59broadband measures of, 27–29CMOS differential pair, 219–20CMOS mixers, 269in common-collector/drain configuration, 213...

  • Page 525

    504IndexMixer noise, 250–59analysis, 255bipolar, 256–58breakdown in RF stage, 256calculations, 253CMOS, 258–59components, 254–56components summary, 256–59dominant sources, 255frequency bands, 251at LO levels, 251matching, 279simulation results, 254Mixer noise figure, 250determination, 2...

  • Page 526

    Index505parallel circuits, 305–7series circuits, 305–7NMOS transistors, 88–90cross coupling, 348defined, 88gate-referred noise, 94operation, 89–90transconductance matching, 349triple well, 89width and length, 349Noise, 7–18SD, 424in amplifiers, 186–203available power, 8bandwidth, 378b...

  • Page 527

    506IndexNonlinearity (continued)in CMOS transistor, 211in common-collector amplifier, 213in diodes, 19exponential, 205–11with first-/third-order terms, 20high-frequency, 213mixer, 259–62mixing with, 239in output impedance of bipolar transistor, 211–13second-order issues, 61–62transmitter,...

  • Page 528

    Index507power amplifiers, 486role, 169Parallel capacitance, 112Parallel coupled quadrature oscillators, 382–87current injection, 384defined, 382design, 385–87illustrated, 383loop gain, 384phase and amplitude, 386phase shift, 387phase to injected signal for, 386two amplifier stages in feedback...

  • Page 529

    508IndexPhase shifts, 271–74differential circuit producing, 272of external signal, 382feedback network, 299injection-locked oscillator, 381–82, 383polyphase filters, 273–74RC networks producing, 271PLL synthesizersSD noise, 424charge pump noise, 423continuous-time analysis, 405–10crystal ...

  • Page 530

    Index509drawbacks, 388modeled as two amplifier stages in feedback, 383model for, 384negative Gm, 383, 387, 388oscillation phase and amplitude, 386parallel coupled, 382–87phase noise, 388phase shift, 387series coupled, 387–88with superharmonic coupling, 388Quadrature phase shift keying (QPSK),...

  • Page 531

    510IndexRing oscillators (continued)five-stage multiple-pass, 371illustrated, 363minimum number of stages, 364model for noise analysis, 365modeling, 364–65phase noise, 370, 373phase noise prediction, 373phase noise versus load capacitance, 375phase noise versus offset frequency, 376single-ended...

  • Page 532

    Index511Supply noise filters, 362–63Switchingbank, 347–49folded, 283LO, 246mixer with, 253modulator analysis, 248–50upper quad, 245–50waveform, 248Switching quad, 242currents from, 244nonlinearity in, 261saturation of, 261Symmetrical saturation, 20Symmetry, transistor layout, 98–99Synth...

  • Page 533

    512IndexTransistors (continued)mixer, 263NMOS, 88–90optimization, 236performance versus bias current, 200PMOS, 88, 90saturation, 480size, 236symmetry, 98–99transconductance, 304typical layout for, 98Transmission lines, 125–26calculation of, 163–64capacitance, 236characteristic impedance, ...

  • Page 534

    Index513Voltage-versus-current transfer function, 208Volterra series, 19Volts-per-volt (V/V), 284WWalking IF architecture, 47Weaver image-reject mixers, 270, 271YYZ Smith chart, 104, 105ZZero temperature coefficient (ZTC), 226, 228