9.1.4 Addressing Devices on the Bus

Chapter 9.1.4 Addressing Devices on the Bus

Physics Lecture Notes – Phys 395 Electronics Book
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Physics Lecture Notes – Phys 395 Electronics Book

  • CHAPTER 9. COMPUTERS AND DEVICE INTERCONNECTION1729.1.4Addressing Devices on the BusThe address determines the destination or source of information. Since the wires of a bus arecommon to all functional units, each unit will see all the data placed on the bus lines. Theaddress lines are used within a receiving unit to determine if available information shouldbe processed or ignored. Each data repository on a common bus will have a unique address.When the CPU needs to transfer data between itself and a particular location, it imple-ments a sequence of signals as specified by the read or write operation protocol for the bus.The range of numbers that can be represented by the available address lines (wires) on a busis known as the address space. A range of numbers is used mostly to access information frommemory and is thus known as the memory address space. Some processors assign a few ofthese memory addresses to other input/output devices. A feature known as memory-mappedI/O.9.1.5Control of the BusThe information flow on the computer bus is time-multiplexed to allow different functionalunits to use the same bus lines at different times. We will assume that only one device triesto write (drive) a given bus line at any time. A special unit, known as a bus master, hasthe responsibility for controlling the other units, which are correspondingly known as thebus slaves. If several units are capable of becoming bus masters these units must arbitrateamongst themselves to determine which is to have control of the bus for a given interval oftime. Often a direct memory access (DMA) unit is allowed to communicate with a slavememory without going through the CPU bus master. This allows memory access at a higherspeed than having to go through the intermediate CPU bus master.9.1.6Clock LinesThe changes of state of all bused signals are synchronized to one or more clock signals, whichare distributed to all functional units on the bus.Read and write operations between the CPU and memory units are the most common.One approach is for the CPU to set the address lines and data lines and then blindly issuethe control pulses, assuming that the slave unit will respond as needed within the allowedtime.A more elegant but slightly slower technique uses a handshake which requires anacknowledgment response from the slave before proceeding.9.1.7Random Access MemoryThe random-access memory (RAM) supports both read and write operations. Integratedcircuit RAM comes in two main types:static RAM in which a single bit of memory is simply a digital flip-flop and requires onlycontinuous power to maintain its state.