9.1.3 Mechanical Arrangement

Chapter 9.1.3 Mechanical Arrangement

Physics Lecture Notes – Phys 395 Electronics Book
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Physics Lecture Notes – Phys 395 Electronics Book

  • CHAPTER 9. COMPUTERS AND DEVICE INTERCONNECTION170• random access storage (memory), and• input/output to external devices (I/O).The sub-units of the CPU are• instruction decode and CPU control,• control of addressing for memory and I/O ports,• data transfer control,• data and address registers and• arithmetic logic unit.To keep track of the CPU steps, the processor maintains a special register, known asthe program counter. The program counter points to (contains the address of) the nextinstruction to be executed. The instruction itself specifies• the operation to be performed,• the processor registers to be used and• possibly data (or a pointer to data in memory).The CPU will typically perform the following execution cycle:1. use the program counter to fetch the next instruction.2. decode the instruction and fetch data from memory into internal registers as required,3. perform the instruction and put the result in another internal register and4. set status bits in the status register as required.The various functional units of the computer are connected by one or more multi-wiredigital buses which pass data, addresses, and control information between the units as shownin figure ArrangementMachines with the lowest cost and highest reliability are generally those with the fewestmechanical connectors and socketed components, while those with more connectors andsockets are more easily expanded and maintained. One design is to have all circuits onmechanically equivalent boards that plug into a common bus, this is the most modulararrangement and is easily maintained. An alternative design is the single-board computerwhich places the CPU and a substantial portion of the memory and I/O interface circuitsonto a single circuit board. This design is more compact and less expensive.