8.5.1 Parallel-Encoding ADC (flash ADC)

Chapter 8.5.1 Parallel-Encoding ADC (flash ADC)

Physics Lecture Notes – Phys 395 Electronics Book
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Physics Lecture Notes – Phys 395 Electronics Book

  • CHAPTER 8. DATA ACQUISITION AND PROCESS CONTROL162000001010011100101110111000001010011100101110111000001010011100101110111DIGITAL INPUTDIGITAL INPUTDIGITAL INPUTa)b)c)ANALOGOUTPUTPERFECTDACANOMALOUSSTEP SIZENON−MONOTONICBEHAVIOUR+1/2 LSB error−3/2 LSB errorFigure 8.3: Output signals from DACs showing a) the ideal result, and b) a differentialnonlinearity or c) non-monotonic behavior, both caused by imperfectly matched resistors.8.5.1Parallel-Encoding ADC (flash ADC)The parallel-encoding or flash ADC design provides the fastest operation at the expense ofhigh component count and high cost (figure 8.5).The resistor network sets discrete thresholds for a number of comparators. All comparatorswith thresholds above the input signal go false while those below go true. Then digitalencoding logic converts the result to a digital number.8.5.2Successive-Approximation ADCThe successive-approximation ADC is the most commonly used design (figure 8.6). Thisdesign requires only a single comparator and will be only as good as the DAC used in thecircuit.The analog output of a high-speed DAC is compared against the analog input signal. Thedigital result of the comparison is used to control the contents of a digital buffer that bothdrives the DAC and provides the digital output word.The successive-approximation ADC uses fast control logic which requires only n compar-isons for an n-bit binary result (figure 8.7).8.5.3Dual-Slope ADCThe limitations associated with the DAC in a successive-approximation ADC can be avoidedby using the analog method of charging a capacitor with a constant current; the time requiredto charge the capacitor from zero to the voltage of the input signal becomes the digitaloutput. When charged by a constant current the voltage on a capacitor is a linear function