CHAPTER 7. DIGITAL CIRCUITS155ENABLEOUTCOUNTCOUNT ENABLEJCKSRQQJCKSRQQJCKSRQQFigure 7.30: A 3-bit synchronous counter.7.13.4Divide-by-N CountersA common feature of many digital circuits is a high-frequency clock with a square waveoutput. If this signal of frequency f drives the clock input of a JKFF wired to toggle oneach trigger, the output of the ﬂip-ﬂop will be a square wave of frequency f/2. This singleﬂip-ﬂop is a divide-by-2 counter. In a similar manner an n ﬂip-ﬂop binary counter will yieldan output frequency that is f divided by 2n.