7.11 Dynamically Clocked Flip-Flops

Chapter 7.11 Dynamically Clocked Flip-Flops

Physics Lecture Notes – Phys 395 Electronics Book
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Physics Lecture Notes – Phys 395 Electronics Book

  • CHAPTER 7. DIGITAL CIRCUITS151JKCQQ00pno change01p0110p1011ptoggleKCJScRcCQNQJCKSRQQDEV1Figure 7.22: The basic JK flip-flop constructed from an RS flip-flop and gates, and itsschematic symbol and truth table.7.11Dynamically Clocked Flip-FlopsWe distinguish two types of clock inputs.static clock input – a clock input sensitive to the signal level anddynamic clock input – a clock input sensitive to signal edges.7.11.1Master/Slave or Pulse TriggeringWe can simulate a dynamic clock input by putting two flip-flops in tandem, one drivingthe other in a master/slave arrangement as shown in figure 7.23. The slave is clocked in acomplementary fashion to the master.SLAVEMASTERKCJSRQNQSRQNQFigure 7.23: An implementation of the master/slave flip-flop.This arrangement is still pulse triggered. The data inputs are written onto the master flip-flop while the clock is true and transferred to the slave when the clock becomes false. Thearrangement guarantees that the QQoutputs of the slave can never be connected to theslave’s own RS inputs. The design overcomes signal racing (ie. the input signals never catchup with the signals already in the flip-flop). There are however a few special states when atransition can occur in the master and be transferred to the slave when the clock is high.These are known as ones catching and are common in master/slave designs.7.11.2Edge TriggeringEdge triggering is when the flip-flop state is changed as the rising or falling edge of a clocksignal passes through a threshold voltage (figure 7.24). This true dynamic clock input is