7.10 Clocked Flip-Flops

Chapter 7.10 Clocked Flip-Flops

Physics Lecture Notes – Phys 395 Electronics Book
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Physics Lecture Notes – Phys 395 Electronics Book

  • CHAPTER 7. DIGITAL CIRCUITS149D+(CoQ)CoQDCDDCQFigure 7.17: An AND-OR gate used as a “ones catching” latch and its timing diagram.SRQQ00no change0101101011undefinedRS flip-flopQNQRSSRQNQFigure 7.18: The RS flip-flop constructed from NOR gates, and its circuit symbol and truthtable.7.10Clocked Flip-FlopsA clocked flip-flop has an additional input that allows output state changes to be synchro-nized to a clock pulse.7.10.1Clocked RS Flip-FlopWe first consider the static clocked (level-sensitive) RS flip-flop shown in figure 7.20. Thesymbol x in the following tables represents either the binary state 0 or 1.The first five lines in the truth table give the static input and output states. The last fourlines show the state of the outputs after a complete clock pulse p.