Introduction to Digital Logic with Laboratory Exercises Book

Introduction to Digital Logic with Laboratory Exercises Book
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Introduction to Digital Logic with Laboratory Exercises Book

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    Introduction to Digital Logicwith Laboratory Exercises

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    Introduction to Digital Logic with Laboratory ExercisesJames FeherCopyright © 2010 James FeherEditor-In-Chief: James FeherAssociate Editor: Marisa DrexelProofreaders: Jackie Sharman, Rachel PuglieseFor any questions about this text, please email:actionURI(mailto:drexel@uga.edu?subject=Digital%20...

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    70,Appendix 70, F: 70, Solutions .............................................................................................................. 70 70,Chapter 1 review 70, exercises.......................................................................................................................

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    Prefacegoal of the Global Text Project initially is to focus on content development and Web distribution, and work with relevant authorities to facilitate dissemination by other means when bandwidth is unavailable or inadequate. The goal is to make textbooks available to the many who cannot affor...

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    1. The transistor and inverterThe breadboardIn order to build the circuit, a digital design kit that contains a power supply, switches for input, light emitting diodes (LEDs), and a breadboard will be used. Make sure to follow your instructor's safety instructions when assembling, debugging, and ...

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    1. The transistor and inverterProcedure1. Write the prelab in your lab notebook for all the circuits required in the steps that follow.2. Obtain instructor approval for your prelab.3. Draw a diagram of the inverter circuit.4. With the power off on your digital trainer, construct your inverter. Up...

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    2. Logic gatesLogic symbolsAs mentioned in the previous lab, NAND and NOR gates can be constructed with fewer components than AND and OR gates. For this reason, the inverter, NAND and NOR make up four of the seven chips used in all of the labs. Symbols used to represent the NAND, NOR, AND, OR and...

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    2. Logic gatesmakes it much easier to construct and demonstrate the circuit. But above all, the greatest benefit comes if the circuit does not work and needs to be debugged! In this case, with all of the pins clearly labeled on your diagram, it is much easier for someone to examine your circuit, ...

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    3. Logic simplificationyields the same result. Designs with fewer chips and wires generally take less time to build, resulting in less expensive, more robust circuits. Similarly, the circuit that implements the XOR from the last chapter could be built with just NAND gates, however as five gates w...

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    3. Logic simplificationIn summary, the procedure for using K-maps to find minimal logical expressions is given below.1. Construct the K-map corresponding to the truth table.2. Circle any 1 that is NOT adjacent (isolated) to any other 1. 3. Find any 1 that is adjacent to only one other. Then circl...

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    3. Logic simplificationCircuit design, construction and debuggingWhile these techniques are useful in minimizing the logical expression, ultimately the circuits still need to be constructed. As the complexity of the circuits increases, it is important to note some of the techniques that can be us...

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    3. Logic simplification(c)(d)Procedure1. Write the prelab in your lab notebook for all the circuits required in the steps that follow.2. Obtain instructor approval for your prelab.3. Build the circuit required for Exercise 5 from the review exercises. (a) Make sure to test each of the portions of...

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    4. More logic simplificationInput placement on K-mapAll of the K-maps shown so far have had the input variables A and B set along the top with the input variables C and D along the side. This does not need to be the case, but it is the convention used here. In addition, the inputs have used the g...

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    4. More logic simplification3. Build the circuit required for Exercise 2(b) from the review exercises. 4. Demonstrate the working circuit for your instructor.5. Repeat the steps from the last procedure for Exercise 2(c) from the review exercises.29

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    5. Multiplexercan be built with a single mux. Note that as mentioned previously, the strobe pin is tied low and the order of the inputs from the function differ from the order of the input lines for the 74151 chip.A'B'00A'B01AB11AB'10C'01011C10101Table 15: g(a,b,c)A B C f0001001001000111100110111...

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    5. MultiplexerExhibit 5.3: h(a,b,c,d) implemented with 8-to-1 muxAs the mux can implement logical functions directly from the truth table without the need for any logic minimization, it is often tempting to use the mux to implement every function and simply skip the minimization techniques descri...

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    6. Timers and clocksSetting V(t) equal to (2/3)Vcc and solving for t yields the time when the output will go low (assume three digits of accuracy).t = 1.10(RC)Note that the values for resistors and capacitors often vary with a tolerance of ±5 per cent and ±10 per cent respectively. Hence, the t...

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    6. Timers and clocksline is brought low, A, B, and the Output all assume an intermediate value as there is no guarantee of how fast the transition will occur. Once at 10.0 nanoseconds, the output of the inverter can be verified to have gone low and the state for A is listed as low. This transitio...

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    6. Timers and clocks3. Assume delay for each logic gate is 10.0 nanoseconds for the circuit in Exhibit 3.3 and that input values of A is low and B and C are all at logic high. Draw a timing diagram for a transition at time zero that takes input for C from logic high to logic low. List input A, B,...

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    7. Memory Exhibit 7.1: SR latchThe NAND based SR latch is an active low device with a default state of logic high for both S and R inputs. The S and R input values are brought low to change the state. Just as the NOR based SR latch should not have both input values turned high simultaneously, the...

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    7. Memory Some devices also come with a PRESET line that can be used to set or turn on the output in much the same manner. These lines can be used to load the flip-flops with specific values, especially when the unit is first powered on. The clock line has a small triangle that denotes that the d...

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    8. State machineswill transition regardless of any input, then no input will be listed next to that arrow. A timing diagram for this four state counter is given in 47, Exhibit 47, 8.2.b. This assumes that the final circuit is clocked at 1.00 seconds and that the rising edge triggered flip-flops a...

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    8. State machines Exhibit 8.5: Counter CircuitExample 2: Four state counter with inputThe four state counter given i 47,n Exhibit 47, 8.2.a 47, introduces a complexity by adding an external input. The state transition diagram is redrawn i 49,n Exhibit 49, 8.6 49, with the states labeled in binary...

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    8. State machineshigh. For testing purposes, a switch can be used for the clock. However, make sure to read the next section regarding debounced switches before using a switch for this purpose. Debounced switchesOne word of caution is in order when using switches as the clock source. As a switch ...

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    9. More state machinesthe memory bits at zero. The 74175 quad D flip-flop in the logic kit does not offer a PRESET pin. However the same type of RC circuit can be used for other flip-flops that do.Assigning unused states to the systemPowering up is not the only time the machine can enter an unuse...

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    9. More state machinesExample 2: Five state machineThe five state machine shown in 56, Exhibit 56, 9.5 56, has two different loops. One of the loops transitions between 000 and 111 while the other goes from 001 to 010 to 100. This leaves three possible states that are unused. The truth table that...

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    9. More state machinesIt should be noted that all of the designs shown in this text have used only the D flip-flop. However, it can often be the case that another type can result in a simpler design. JK flip-flops can be used to produce ripple counters with minimal extra circuitry. The JK flip-fl...

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    Appendix A: Chip pinoutsExhibit A.4: 7410Exhibit A.5: 7415162

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    Appendix A: Chip pinouts555 TimerExhibit A.7: 555 timer 64

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    Appendix B: Resistors and capacitorscode. The tolerances will not be utilized in this lab manual. Another example is provided in 66,Exhibit 66, B.2. Applying the formula to obtain the value for this resistor is left as an exercise for the reader.Exhibit B.2: 100,000 Ohm ResistorCapacitorsIn dire...

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    Appendix F: Solutions 5. The ground symbol is given here. 6. The NAND is the opposite of the AND gate. The function has two different variables, each with two distinct answers (T-1 or F-0), so there should be four (22) different possibilities for the function.AB(AB)'0010111011107. AB(A+B)'00101...

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    Appendix F: Solutions e. y(A,B) = A' + B A BA'y0011011110001101f. y(A,B,C) = ((A+B)'(B+C)')'ABCA+BB+C(A+B)'(B+C)'(A+B)'(B+C)'y000001110001011001010110001011110001100100101101110001110110001111110001Another example of a logic function with a different equivalent, (A + B + C).4. Solution with pi...

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    Appendix F: Solutions A'B'00A'B01AB11AB'10C'D'001001C'D011001CD110000CD'100000Group spanning boundaryA'B'00A'B01AB11AB'10C'D'001001C'D010000CD110000CD'101001Four corner groupA'B'00A'B01AB11AB'10C'D'001111C'D011111CD110000CD'100000Group of eight3. Truth tables follow.a. f(A,B,C) = AB + A'BC' + A...

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    Appendix F: Solutions 4. Minimal expressions given for each map. Notice that quite often, the terms in the original are not found at all in the minimal SOP (Sum Of Products) expression.a. Original expression: f(A,B,C) = AB + A'BC' + AB'C Minimal expression: f(A,B,C) = BC' + ACb. Original exp...

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    Appendix F: Solutions b. Minimal expression: C' + A'BDirect implementation from circuitDe Morgan's lawDouble negatives cancelDe Morgan's lawDouble negativesc. Two different Minimal expressions exist for this problem.i. Minimal expression: C'D' + A'C' + BC' + AC ii. Minimal expression: C'D' + ...

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    Appendix F: Solutions b. Minimal expression: A + C c. Notice that this solution has one of the groupings that spans the boundaries (B'C).Minimal expression: AB'+ AD + B'C d. This expression includes the four corner grouping (B'D').Minimal expression: B'D' + A'B e. Two different Minimal expre...

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    Appendix F: Solutions c. Minimal expression: BD + AD + A'B'C d. Minimal expression: CD' + AD' Chapter 5 review exercises1. K- map and minimal SOP expressionsa. f1(a,b,c) = a'b'c' + a'bc' + a'bc + ab'c' Minimal expression: f1(a,b,c) = a'b + b'c' abcf10001001001010111100110101100111083

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    Appendix F: Solutions d. f4(a,b,c,d) = a'b'c'd' + a'bc'd + abcd + a'b'cd' + a'b'cd + a'bcd' + ab'c'dMinimal expression: f4(a,b,c,d) = a'b'c + a'cd' + a'b'd' + abcd + a'bc'd + ab'c'd a b c df4Mux In0 0 0 01d'0 0 0 10d'0 0 1 0110 0 1 1110 1 0 00d0 1 0 11d0 1 1 01d'0 1 1 10d'1 0 0 00d1 0 0 11d1 0 ...

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    This book is licensed under aactionURI(http://creativecommons.org/licenses/by/3.0/): CreativeactionURI(http://creativecommons.org/licenses/by/3.0/): CommonsactionURI(http://creativecommons.org/licenses/by/3.0/): Attribution 3.0actionURI(http://creativecommons.org/licenses/by/3.0/): License2. f2(...

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    Appendix F: Solutions 4. Circuit design a. g1(a,b,c,d) = a'b'c'd + abcd + a'bcd + a'bc'd + ab'c'd + a'b'cd + abc'd + ab'cdMinimal expression: g1(a,b,c,d) = dWhen the K-map is filled out, it can be seen that the minimal solution is simply d. No logic is needed at all! Hopefully, you did not try ...

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    This book is licensed under aactionURI(http://creativecommons.org/licenses/by/3.0/): CreativeactionURI(http://creativecommons.org/licenses/by/3.0/): CommonsactionURI(http://creativecommons.org/licenses/by/3.0/): Attribution 3.0actionURI(http://creativecommons.org/licenses/by/3.0/): Licensec. g3(...

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    Appendix F: Solutions d. g4(a,b,c,d) = a'bc'd' + abc'd' + abcd' + ab'cd' + a'bc'd + abc'd + abcd + ab'cdMinimal expression: bc' + ac Chapter 6 review exercises1. Periods in seconds of the clock with given frequenciesa. T = 1/f T = 1/(6,000,000) = 0.000000167 sec or 167 nsecb. T = 1/(10,000,...

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    This book is licensed under aactionURI(http://creativecommons.org/licenses/by/3.0/): CreativeactionURI(http://creativecommons.org/licenses/by/3.0/): CommonsactionURI(http://creativecommons.org/licenses/by/3.0/): Attribution 3.0actionURI(http://creativecommons.org/licenses/by/3.0/): License3. Not...

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    Appendix F: Solutions c. The schematic should look identical to Exhibit 6.1 with the appropriate values for R and C.d. Last, for the values chosen, the span for the times is calculated below.i. 1 second timer:1.10(0.95 * 9400)(0.9 * 100u) < actual < 1.10(1.05 * 9400)(1.1 * 100u).89 <...

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    Appendix F: Solutions 2. For the SR latch constructed with NAND gates, recall that the NAND gate will have an output of 1 if either of the input values is 0. In this manner, some of the next state values may be determined immediately.Now, the remaining undetermined rows are examined. SR Q Q' QNQ...

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    This book is licensed under aactionURI(http://creativecommons.org/licenses/by/3.0/): CreativeactionURI(http://creativecommons.org/licenses/by/3.0/): CommonsactionURI(http://creativecommons.org/licenses/by/3.0/): Attribution 3.0actionURI(http://creativecommons.org/licenses/by/3.0/): LicenseD C Q Q...

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    Appendix F: Solutions DCLEARQ000010100111Chapter 8 review exercises1. Because switches suffer from bounce, the circuit could interpret the bounces as clock pulses as well. This would mean that the circuit might be clocked more than once for a given flip of the switch.2. 3. 95

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    This book is licensed under aactionURI(http://creativecommons.org/licenses/by/3.0/): CreativeactionURI(http://creativecommons.org/licenses/by/3.0/): CommonsactionURI(http://creativecommons.org/licenses/by/3.0/): Attribution 3.0actionURI(http://creativecommons.org/licenses/by/3.0/): License4. Two...

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    Appendix F: Solutions 7. The state machine has 3 states so it requires 2 flip-flops.21 < 3 <= 22The state 11 is not used. The next chapter will discuss the design of systems with unused states.Chapter 9 review exercises1. A state machine that has 7 states will require 3 flip-flops. 22 &l...

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    Appendix F: Solutions a. b. Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'00001Q2 10111Q2N(Q2,Q1,Q0) = Q1Q0' + Q2Q0 Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'00111Q2 10001Q1N(Q2,Q1,Q0) = Q1Q0' + Q2'Q0 Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'01100Q2 10011Q0N(Q2,Q1,Q0) = Q2'Q1' + Q2Q16. A two bit counter is to be built that will...

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