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Introduction to Digital Logicwith Laboratory Exercises

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This book is licensed under a Creative Commons Attribution 3.0 LicenseIntroduction to Digital Logic withLaboratory ExercisesJames FeherCopyright © 2009 James FeherEditor-In-Chief: James FeherAssociate Editor: Marisa DrexelProofreaders: Jackie Sharman, Rachel PuglieseFor any questions about this ...

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Table of ContentsPreface...............................................................................................................................................................70. Introduction.....................................................................................................

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This book is licensed under a Creative Commons Attribution 3.0 LicenseAppendix C: Lab notebook.........................................................................................................71Appendix D: Boolean algebra........................................................................

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Index of TablesTable 1: NAND table...................................................................................................................15Table 2: NOR table.....................................................................................................................15Table 3: ...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseAbout the author and reviewersAuthor: James FeherJim currently teaches computer science at McKendree University in Lebanon, Illinois. He is a huge open sourcesoftware proponent. His research focuses on the use of open source s...

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This book is licensed under a Creative Commons Attribution 3.0 LicensePrefaceThis lab manual provides an introduction to digital logic, starting with simple gates and building up to statemachines. Students should have a solid understanding of algebra as well as a rudimentary understanding of basi...

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Prefacework with the Global Text project to develop this text. The Global Text Project will create open content electronictextbooks that will be freely available from a website. Distribution will also be possible via paper, CD, or DVD. Thegoal of the Global Text Project initially is to focus on c...

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This book is licensed under a Creative Commons Attribution 3.0 License0. IntroductionIt is nearly impossible to find a part of society that has not been touched by digital electronics Obviousapplications such as computers, televisions, digital video reorders and countless other consumer electroni...

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This book is licensed under a Creative Commons Attribution 3.0 License1. The transistor andinverterLearning objectives• Use the digital trainer and breadboard.• Assemble a circuit.• Build a logic circuit with discrete components.The transistorA transistor is a three-terminal device that can...

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1. The transistor and inverterThe breadboardIn order to build the circuit, a digital design kit that contains a power supply, switches for input, light emittingdiodes (LEDs), and a breadboard will be used. Make sure to follow your instructor's safety instructions whenassembling, debugging, and ob...

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This book is licensed under a Creative Commons Attribution 3.0 License• Always make sure to have a clearly documented circuit diagram before you start wiring the circuit.The inverterThe inverter, sometimes referred to as a NOT gate, is a simple digital circuit requiring one transistor and twore...

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1. The transistor and inverter5. Construct a truth table for a NAND gate.6. Construct a truth table for a NOR gate.Procedure1. Write the prelab in your lab notebook for all the circuits required in the steps that follow.2. Obtain instructor approval for your prelab.3. Draw a diagram of the invert...

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This book is licensed under a Creative Commons Attribution 3.0 License2. Logic gatesLearning objectives• Use 7400 series chips in designing digital logic functions.• Draw complete circuit diagrams.• Construct and debug digital logic circuits using 7400 series chips.History of logic chipsLog...

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2. Logic gatesLogic symbolsAs mentioned in the previous lab, NAND and NOR gates can be constructed with fewer components than ANDand OR gates. For this reason, the inverter, NAND and NOR make up four of the seven chips used in all of the labs.Symbols used to represent the NAND, NOR, AND, OR and i...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseExhibit 2.9: NAND inverter yields ANDExhibit 2.10: NAND NAND to yield ANDLogical functionsExhibit 2.11 demonstrates how to implement a simple logical expression using the gates provided. Make sure touse only those gates that ar...

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2. Logic gatesthe respective inputs and outputs. All of this makes it much easier to construct and demonstrate the circuit. Butabove all, the greatest benefit comes if the circuit does not work and needs to be debugged! In this case, with all ofthe pins clearly labeled on your diagram, it is much...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseReview exercises1. If a logic function has three inputs, how many rows must the truth table have to contain all possiblestates? Justify your answer.2. Repeat the last problem for five inputs.3. For the following functions, cons...

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This book is licensed under a Creative Commons Attribution 3.0 License3. Logic simplificationLearning objectives• Use reduction techniques to obtain minimal functional representations.• Design minimal three and four input logical functions.• Build and debug three and four input logical func...

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3. Logic simplificationNotice that the first expression exactly matches the function that was built in the previous chapter using twoNANDs, one NOR and three inverters. The new circuit shown in Exhibit 3.3 implements the same expression withjust three NAND gates. This results in a design using on...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseExamine the expression f(A,B,C) = ABC + ABC' + A'BC + A'BC'. As listed, it requires four three-input AND gates,one four-input OR gate and several inverters. The truth table is copied over to the eight cell K-map below. Noticeth...

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3. Logic simplificationIn summary, the procedure for using K-maps to findminimal logical expressions is given below.1. Construct the K-map corresponding to thetruth table.2. Circle any 1 that is NOT adjacent (isolated)to any other 1. 3. Find any 1 that is adjacent to only one other1. Circle these...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseIn step 2, above, the 1 in thebottom right is shaded. In step 3, to the left, the pair oftwo 1s in the second column isshaded. Note that the bottom itemA'BCD dictates that this group iscircled. The top item, A'BC'D hasmany diff...

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3. Logic simplificationCircuit design, construction and debuggingWhile these techniques are useful in minimizing the logical expression, ultimately the circuits still need to beconstructed. As the complexity of the circuits increases, it is important to note some of the techniques that can beusef...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseDEBUGGING TIP: Do not allow yourself to get frustrated! This is easier said than done, butgetting upset does not serve any purpose in effective troubleshooting. If you have done all of the above and things still do not work:•...

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3. Logic simplification6. For 3(c), design the circuit for the minimal SOP expression found in problem 4 using just NANDgates and inverters. Label the pinouts on the circuit diagram.7. Given each of the K-maps, determine the minimal expression associated with it.(a)(b)(c)(d)Procedure1. Write the ...

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This book is licensed under a Creative Commons Attribution 3.0 License4. More logic simplificationLearning 0bjectives• Review all possible K-map groupings.• Use “don't care” conditions in minimization.Additional K-map groupingsSome of the rectangular groupings allowed for Karnaugh maps, s...

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4. More logic simplificationdespite the ordering of the input variables. In Exhibit 4.5 the same function is represented as in Exhibit 4.3. In thiscase, the region highlighted for D' does not span two boundaries, while the grouping for A'C' does in this format.Again, it can be shown that the same...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseReview exercises1. Given each of the K-maps, determine the minimal SOP expression. d represents a don't care condition.(a)(b)(c) (d)(e)(f)2. For the functions listed below, construct a K-map and determine the minimal SOP e...

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4. More logic simplificationProcedure1. Write the prelab in your lab notebook for all the circuits required in the steps that follow.2. Obtain instructor approval for your prelab.3. Build the circuit required for Exercise 2(b) from the review exercises. 4. Demonstrate the working circuit for your...

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This book is licensed under a Creative Commons Attribution 3.0 License5. MultiplexerLearning objective• Use the multiplexer to implement complex logical functions.Background on the “mux”A multiplexer, often just called a mux, is a device that can select its output from a number of inputs. T...

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5. Multiplexercorresponding outputs. Note that the value of data lines D0, D3, D4, D5, and D6, which also are found on pins 4, 1,15, 14, and 13 are set to high with the remaining data lines set low. In this manner, any three input logical functionscan be built with a single mux. Note that as ment...

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This book is licensed under a Creative Commons Attribution 3.0 Licensechips to implement, such as the function h(a,b,c,d) found in the K-map and truth table that follow. Two differentminimal SOP expressions exist for this function.h(a,b,c,d) = a'bc' + a'b'c + acd' + ab'c'd + a'c'd'h(a,b,c,d) = a'...

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5. MultiplexerAs the mux can implement logical functions directly from the truth table without the need for any logicminimization, it is often tempting to use the mux to implement every function and simply skip the minimizationtechniques described earlier. Resist this temptation! Often the minima...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseReview exercises 1. Construct the truth table and K-map for each of the following functions and determine the minimal SOPexpression.(a) f1(a,b,c) = a'b'c' + a'bc' + a'bc + ab'c'(b) f2(a,b,c) = a'b'c + a'bc + abc' + ab'c(c) f3(a...

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This book is licensed under a Creative Commons Attribution 3.0 License6. Timers and clocksLearning objectives• Review relation between time and frequency.• Construct timer and clock circuits.• Produce a timing digram for a circuit.Timing in digital circuitsTiming circuits are often required...

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6. Timers and clocksV(t) = Vcc( 1 – e-(t/rc)) Setting V(t) equal to (2/3)Vcc and solving for t yields the time when the output will go low (assume three digits ofaccuracy).t = 1.10(RC)Note that the values for resistors and capacitors often vary with a tolerance of ±5 per cent and ±10 per cent...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseExhibit 6.3 shows a clock circuit using the 555 timer. When configuredin this manner, it is said that the timer is operating in astable mode. Thismeans that there is no stable state for the circuit; it just continues tooscillat...

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6. Timers and clocksmaximum delay of 10.0 nanoseconds. This mayvary depending upon the logic family used, so thedata sheet should be consulted for verificationwhen determining the maximum delay for a givencircuit. Notice that once the SELECT line isbrought low, A, B, and the Output all assume ani...

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This book is licensed under a Creative Commons Attribution 3.0 Licensemeasurements used is understood, it is important to remember the rules that apply to the number of significantdigits for any calculation.• Trailing zeros are significant to the number.• Use all digits when performing calcul...

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6. Timers and clocks(a)10.0 μsec(b)0.0500 nanoseconds (c)1.00 milliseconds3. Assume delay for each logic gate is 10.0 nanoseconds for the circuit in Exhibit 3.3 and that input values ofA is low and B and C are all at logic high. Draw a timing diagram for a transition at time zero that takes inpu...

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This book is licensed under a Creative Commons Attribution 3.0 License7. Memory Learning objectives• Review differences between logic circuits and persistent memory.• Review properties for the S-R latch and D flip-flop.• Construct a circuit using a flip-flop.MemoryYou have often heard the p...

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7. Memory Latches can also be built using NAND gates, but the set and reset lines operate in a slightly different manner underthis configuration. The transitions for these latches are examined in more detail in the exercises.Exhibit 7.1: SR latchThe NAND based SR latch is an active low device wit...

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This book is licensed under a Creative Commons Attribution 3.0 Licensetransition and the time before the next clock pulse should last long enough for the output state to stabilize.Manufacture specifications for the device being used should be consulted to determine the maximum clock speed.Since t...

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7. Memory 1. Use the SR latch from Exhibit 7.1. Assuming the values in the table represent values that have just occurred,determine the stable values for the outputs QN and QN'. Recall that the NOR gate is an active high gate,meaning any time either of the input values is high the output is low. ...

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This book is licensed under a Creative Commons Attribution 3.0 License• Remember the NAND is an active low device, meaning the output will be 1 if either input is 0 (low).• D and C are 0, so NAND1 and NAND2 will be 1. • NAND3 is 0 and NAND2 is 1, making NAND4 1.• NAND1 is 1 and NAND4 is 1...

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This book is licensed under a Creative Commons Attribution 3.0 License8. State machinesLearning objectives• Construct state transition diagrams.• Relate the number of memory bits required for a given state machine.• Build four state, state machines.What is a state machine?A state machine, o...

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8. State machineswill transition regardless of any input, then no input will belisted next to that arrow. A timing diagram for this four statecounter is given in Exhibit 8.2.b. This assumes that the finalcircuit is clocked at 1.00 seconds and that rising edgetriggered flip-flops are used. Note th...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseFinally, the flip-flops will need to be clocked. In these labs we want to observe the states, so the clock used has aslow period such as 2 seconds and a frequency of ½ hertz. Example 1: Four state counterThe steps that follow ...

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8. State machinesExample 2: Four state counter with inputThe four state counter given in Exhibit 8.2.a introduces a complexity by adding an external input. The statetransition diagram is redrawn in Exhibit 8.6 with the states labeled in binary, Q1 being the most significant bit. Thetruth table us...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseQ1N = x'Q1'Q0 + xQ1 + Q1Q0'= ((x'Q1'Q0)' (xQ1)' (Q1Q0')' )'Q0N = xQ0 + x'Q0'= ((xQ0)' (x'Q0')')'Exhibit 8.7: Circuit diagram for four state counter with inputThe logic is then implemented using the 7400 series chips, as shown i...

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8. State machinesthe CLEAR line will be discussed in more detail in the next chapter. For now the CLEAR will just be tied to logichigh. For testing purposes, a switch can be used for the clock. However, make sure to read the next sectionregarding debounced switches before using a switch for this ...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseReview exercises1. How could using a regular switch as the clock source affect the operation of the counter?2. Draw a timing diagram for the machine that uses the state transition diagram found in Exhibit 8.3.Assume that the ma...

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This book is licensed under a Creative Commons Attribution 3.0 License9. More state machinesLearning objectives• Relate number of states to required amount of memory.• Insure state machines do not enter illegal states.How many bits of memory does a state machine need?The amount of memory or n...

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9. More state machinesthe memory bits at zero. The 74175 quad D flip-flop in the logic kit does not offer a PRESET pin. However the sametype of RC circuit can be used for other flip-flops that do.Assigning unused states to the systemPowering up is not the only time the machine can enter an unused...

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This book is licensed under a Creative Commons Attribution 3.0 License Approach 2: Using don't care conditionsThe next approach instead places don't care conditions for the state 11 as seen in the K-maps below. By selectingthe minimal expressions, the next states for Q1 and Q0 can be found. The r...

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9. More state machinesExample 2: Five state machineThe five state machine shown in Exhibit 9.5 has two different loops. One of the loops transitions between 000and 111 while the other goes from 001 to 010 to 100. This leaves three possible states that are unused. The truthtable that follows uses ...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseQ2N = x'Q2'Q0' + Q2'Q1Q0' Q1N = x'Q2'Q1'Q0' + xQ2'Q1'Q0Q0N = Q1'Q0'Now, if the don't care conditions are used in the design for theminimal expressions, the complexity of the results is reduced.Q2N = x'Q2'Q0' + Q2'Q1or x'Q2'Q0'...

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9. More state machinesIt should be noted that all of the designs shown in this text have used only the D flip-flop. However, it can oftenbe the case that another type can result in a simpler design. JK flip-flops can be used to produce ripple counterswith minimal extra circuitry. The JK flip-flop...

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This book is licensed under a Creative Commons Attribution 3.0 License(b) What are the unused states?(c) Modify the diagram if the unused states transition to 000.(d) Assuming a state machine were to be built using D flip-flops, determine the value of the next state foreach of the flip-flops.5. T...

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This book is licensed under a Creative Commons Attribution 3.0 License10. What's next?Hopefully, this introduction has whetted your appetite for this fascinating subject. Modern technology simplywould not be possible without the advances and applications of this subject in the world in which we l...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseAppendix A: Chip pinoutsIntroduction to Digital Logic with Laboratory Exercises62 A Global Text

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Appendix A: Chip pinouts63

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This book is licensed under a Creative Commons Attribution 3.0 LicenseIntroduction to Digital Logic with Laboratory Exercises64 A Global Text

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Appendix A: Chip pinouts555 TimerA.7: 555 timer 65

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This book is licensed under a Creative Commons Attribution 3.0 LicenseAppendix B: Resistors andcapacitorsResistorsResistors are electronic components that obey Ohm's law: Voltage across a resistor is equal to the currentthrough the resistor times the resistance of the device. V = I * RResistance ...

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Appendix B: Resistors and capacitorslab manual. Another example is provided in Exhibit B.2. Applying the formula to obtain the value for this resistor isleft as an exercise for the reader.Exhibit B.2: 100,000 Ohm ResistorCapacitorsIn direct current circuits, capacitors can be thoughtof as charge ...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseAppendix C: Lab notebookThe lab notebook should be a bound notebook, much like a standard composition notebook. The lab notebook isused to document the experiment or lab procedure. Notebooks can serve many purposes: for the aut...

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Appendix C: Lab notebookWhile following these guidelines certainly makes it easier for your instructor to review your work, that is not itsmain purpose. Keep in mind, someone should be able to understand what you did and even replicate your workgiven your lab notebook. Your lab notebook can be a ...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseAppendix D: Boolean algebraCommutative law: x + y = y + xxy = yxAssociative law:x + (y + z) = (x + y) + zx(yz) = (xy)zDistributive law:x(y + z) = xy + xzx + (yz) = (x + y)(x + z)Absorption:x + (xy) = xx(x + y) = xDe Morgan's la...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseAppendix E: Equipment listQuantityItemDescription1Digital TrainerSee detailed description below.2pn2222 transistorsOther general purpose npn transistors may be substituted.21KΩ 1/4 watt resistors233KΩ 1/4 watt resistors24.7...

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Appendix E: Equipment list7400 series familiesSeveral of the 7400 series families are acceptable for use with these labs. The LS (Low Powered Schottky), ALS(Advanced Low Powered Schottky) or HC (High speed CMOS) are all widely available, relatively inexpensive andwill all perform acceptably.72

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This book is licensed under a Creative Commons Attribution 3.0 LicenseAppendix F: Solutions Chapter 1 review exercises1. Exhibit 1.3 contains the diagram illustrating the commonly connected pins on the breadboard.2. xx!01103. Resistor color codes are explained in detail in Appendix B.(a)(b)(c)Int...

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Appendix F: Solutions (d)4. The ground symbol is given below.5. The NAND is the opposite of the AND gate. The function has two different variables, each with twodistinct answers (T-1 or F-0), so there should be four (22) different possibilities for the function.AB(AB)'0010111011106. AB(A+B)'00101...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseChapter 2 review exercises1. A logic function with three inputs has eight rows because each of the three inputs has two possibilities.(number of possible outcomes for each input)(number of inputs) = 232. A function with five in...

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Appendix F: Solutions (d) y(A,B,C) = (A⨁B)C'A B CA⨁BC'y000010001000010111011100100111101100110010111000(e) y(A,B) = A' + BA BA'y0011011110001101(f) y(A,B,C) = ((A+B)'(B+C)')'ABCA+BB+C(A+B)'(B+C)'(A+B)'(B+C)'y000001110001011001010110001011110001100100101101110001110110001111110001Another ex...

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This book is licensed under a Creative Commons Attribution 3.0 License4. Solution with pinout below. 5. Solution with pinout below. It is optional to label Vcc and Gnd on the diagram. Most often for a chip, theVcc is the upper most right pin and the Gnd is the bottom left, however the chip pinout...

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Appendix F: Solutions Chapter 3 review exercises1. ( (AB)' + (CD)' )(AB)'' (CD)''(AB)(CD)ABCDOriginal CircuitDe Morgan's lawDouble negatives cancelParenthesis not necessary2. Singletons have only one element. Doubles are 2x1 rectangles. Groups of four take two forms, a 4x1rectangle or a 2x2 squar...

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This book is licensed under a Creative Commons Attribution 3.0 License3. Truth tables follow.(a) f(A,B,C) = AB + A'BC' + AB'CA B CABA'BC' AB'Cf0 0 000000 0 100000 1 001010 1100001 0 000001 0 1001111 010011111001(b) g(A,B,C) = A'C + ABC + AB'A B CA'CABCAB'g0 0 000000 0 110010 1 000000 1 110011 0...

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Appendix F: Solutions d) j(A,B,C,D) = A'C'D' + C'D + CDABCDA'C'D'C'DCDj000010010001010100100000001100110100100101010101011000000111001110000000100101011010000010110011110000001101010111100000111100114. Minimal expressions given for each map. Notice that quite often, the terms in the original are...

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This book is licensed under a Creative Commons Attribution 3.0 License(c) Original Expression: h(A,B,C,D) = A'BC' + (A ⨁ B)C + A'B'C'D + ABCDMinimal Expression: h(A,B,C,D) = A'B + A'C'D + BCD + AB'CMinimal Expression: h(A,B,C,D) = A'B + A'C'D + ACD + AB'CMore than one minimal expression exists...

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Appendix F: Solutions 6. h(A,B,C,D) = A'B + A'C'D + BCD + AB'C7. As the logic kit does not contain a four input NAND gate, combinations of three and two input NANDs areused. The following justification shows that this is indeed a correct implementation.8. (a) Minimal Expression: A' + B'(b) Mini...

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This book is licensed under a Creative Commons Attribution 3.0 License(d) Three different minimal expressions exist for this problem.Minimal Expression:Minimal Expression:A'C'D + A'BD + A'CD' + AB'DB'C'D + A'BD + A'CD' + AB'DMinimal Expression:A'C'D + A'BC + A'CD' + AB'DIntroduction to Digital L...

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Appendix F: Solutions Chapter 4 review exercises1. (a) Minimal Expression: B' + AC' (b) Minimal Expression: A + C(c) Notice that this solution has one of the groupings that spans the boundaries (B'C).Minimal Expression: AB'+ AD + B'C (d) This expression includes the four corner grouping (B'D').Mi...

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This book is licensed under a Creative Commons Attribution 3.0 License(e) Two different minimal expressions exist for this problem.Minimal Expression:Minimal Expression:B'C' + A'C' + BCB'C' + A'B + BC(f) Minimal Expression:C'D + A'D'2. (a) Minimal Expression: AB + A'C'(b) Notice that not all don'...

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Appendix F: Solutions (c) Minimal Expression: BD + AD + A'B'C(d) Minimal Expression: CD' + AD'86

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This book is licensed under a Creative Commons Attribution 3.0 LicenseChapter 5 review exercises1. (a) f1(a,b,c) = a'b'c' + a'bc' + a'bc + ab'c'Minimal Expression: f1(a,b,c) = a'b + b'c'abcf100010010010101111001101011001110(b) f2(a,b,c) = a'b'c + a'bc + abc' + ab'cMinimal Expression: f2(a,b,c) ...

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Appendix F: Solutions (d) f4(a,b,c,d) = a'b'c'd' + a'bc'd + abcd + a'b'cd' + a'b'cd + a'bcd' + ab'c'dMinimal Expression:f4(a,b,c,d) = a'b'c + a'cd' + a'b'd' + abcd + a'bc'd + ab'c'dThe truth table also shows the inputs required for the multiplexerwhich will be used later when implementing the fun...

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This book is licensed under a Creative Commons Attribution 3.0 License4. (a) g1(a,b,c,d) = a'b'c'd + abcd + a'bcd + a'bc'd + ab'c'd + a'b'cd + abc'd + ab'cdMinimal Expression: g1(a,b,c,d) = dWhen the K-map is filled out, it can be seen that the minimal solution is simply d. No logic is needed at...

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Appendix F: Solutions (b) g2(a,b,c,d) = a'bc'd + a'b'cd' + ab'cdFor this problem, first the K-map shows that this is the minimal expression. Then the truth table isconstructed to determine the input values for an 8-to-1 mux implementation. a'b'00a'b01ab11ab'10c'd'000000c'd010100cd110001cd'101000a...

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This book is licensed under a Creative Commons Attribution 3.0 License(d) g4(a,b,c,d) = a'bc'd' + abc'd' + abcd' + ab'cd' + a'bc'd + abc'd + abcd + ab'cdMinimal Expression: bc' + acIntroduction to Digital Logic with Laboratory Exercises91 A Global Text

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Appendix F: Solutions Chapter 6 review exercises1. (a)T = 1/fT = 1/(6,000,000) = 0.000000167 sec or 167 nsec(b)T = 1/(10,000,000) = 0.0000001 sec or 100 nsec(c) f = 6000 cycles/min * 1min/60sec = 100 HzT = 1/100 = 0.01 sec or 10.0 msec2. (a)f = 1/Tf = 1/(.00001) = 100 Khz(b)f = 1/(0.00000000005)...

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This book is licensed under a Creative Commons Attribution 3.0 License5. (a) Recall that the timer has a delay of: t = 1.10(RC)Solving for R yields:R = t/(1.10C)The required values for R are found in the table, along with those that are easiest to obtain using the resistors from the lab kit. (b) ...

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Appendix F: Solutions (b) Time on for the 1 second clock is 0.65 seconds and off is 0.33, while time on for the 5 second clock is 2.6 seconds and off is 2.3 seconds.(c) The schematic will look exactly like Exhibit 6.3 with the appropriate R and C values inserted.94

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This book is licensed under a Creative Commons Attribution 3.0 LicenseChapter 7 review exercises1. Recall, if either of the input values are 1, the output of the gate is 0. Whilethe output values of Q and Q' may change, the input values of S and R willnot for this table. So, for any row that ha...

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Appendix F: Solutions Rows 1 & 2: Both QN and QN ' are 1, not inverses of one another.These states are not used.Rows 3 & 4: QN is 1 and R is 1, so QN ' will be 0. These are the set states.Rows 5 & 6: QN ' is 1 and S is 1, so QN will be 0. These are the reset states.Row 7: S and Q'...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseNAND2, there is never a time when the inputs reach a state that should not be used, as with the SR latches thatmust avoid certain states. So when C is low, the state remains constant and when C is high, the state tracks the Din...

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Appendix F: Solutions Chapter 8 review exercises1. Because switches suffer from bounce, the circuit could interpret the bounces as clock pulses as well. Thiswould mean that the circuit might be clocked more than once for a given flip of the switch.2.3. 4. Two flip-flops are needed to represent al...

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This book is licensed under a Creative Commons Attribution 3.0 LicenseThe minimal expression for Q1N is xQ1'Q0' + x'Q1'Q0 + xQ1Q0 + x'Q1Q0 which is not very minimal. For thisreason, the design that follows uses a multiplexer to implement the input for the second flip-flop. The first flip-floprequ...

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Appendix F: Solutions 7. The state machine has 3 states so it requires 2 flip-flops. 21 < 3 <= 22The state 11 is not used. The next chapter will discuss the design of systems with unused states.100

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This book is licensed under a Creative Commons Attribution 3.0 LicenseChapter 9 review exercises1. (a) A state machine that has 7 states will require 3 flip-flops.22 < 7 <= 23(b) With no external inputs, only the existing states provide input to determine the next state, so the K-maps will...

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Appendix F: Solutions (b) Of the 8 possible states, 101 and 100 are not represented.(c) (d)Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'00010Q2 10011Q2N(Q2,Q1,Q0) = Q1Q0 + Q2Q1Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'00110Q2 10010Q1N(Q2,Q1,Q0) = Q1Q0 + Q2'Q0Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'01110Q210000Q0N(Q2,Q1,Q0) = Q2'Q...

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This book is licensed under a Creative Commons Attribution 3.0 License(b)Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'00001Q2 10111Q2N(Q2,Q1,Q0) = Q1Q0' + Q2Q0Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'00111Q2 10001Q1N(Q2,Q1,Q0) = Q1Q0' + Q2'Q0Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10Q2'01100Q2 10011Q0N(Q2,Q1,Q0) = Q2'Q1' + Q2Q16. (a...

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Appendix F: Solutions 7. (a)(b)Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'00110x10101Q1N(x,Q1,Q0) = x'Q0 + Q1'Q0 + xQ1Q0 Q1'Q0'00Q1'Q001Q1Q011Q1Q0'10x'01100x11001Q0N(x,Q1,Q0) = x'Q1' + xQ0'104

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This book is licensed under a Creative Commons Attribution 3.0 LicenseIndex555..............................................................................................................................................7, 37pp., 52, 747400 series.....................................................